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STM32F401RBT6

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by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f401rbt6factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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STM32F401RBT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F401RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup domain supply voltage (1.65 to 3.6 V) for RTC, backup registers, and external oscillator when VDD is absent.
2 PC13 bidirectional GPIO Port C pin 13 (5 V tolerant) with RTC event/tamper and output capability for 5 V I/O level on backup power domain.
3 PC14-OSC32_IN bidirectional GPIO Port C pin 14 or 32 kHz oscillator input (5 V tolerant) for low-speed external crystal resonator.
4 PC15-OSC32_OUT bidirectional GPIO Port C pin 15 or 32 kHz oscillator output (5 V tolerant) for low-speed external crystal resonator.
5 PH0-OSC_IN bidirectional GPIO Port H pin 0 or main oscillator input (5 V tolerant) for 4-26 MHz external crystal or clock source.
6 PH1-OSC_OUT bidirectional GPIO Port H pin 1 or main oscillator output (5 V tolerant) for 4-26 MHz external crystal or clock source.
7 NRST bidirectional Bidirectional reset pin with embedded weak pull-up (30-50 kΩ) and 100 ns input filtering; external capacitor recommended.
8 PC0 bidirectional GPIO Port C pin 0 (5 V tolerant) with ADC1 input channel 10 capability.
9 PC1 bidirectional GPIO Port C pin 1 (5 V tolerant) with ADC1 input channel 11 capability.
10 PC2 bidirectional GPIO Port C pin 2 (5 V tolerant) with SPI2/I2S2 MISO and ADC1 channel 12 capability.
11 PC3 bidirectional GPIO Port C pin 3 (5 V tolerant) with SPI2/I2S2 MOSI and ADC1 channel 13 capability.
12 VSSA/VREF- power_in Analog ground and negative reference for ADC; must be connected to VSS with decoupling capacitors.
13 VDDA/VREF+ power_in Analog supply and positive reference for ADC (1.7-3.6 V); must be connected to VDD with decoupling capacitors and close to device.
14 PA0 bidirectional GPIO Port A pin 0 (5 V tolerant) with USART2/Timer/ADC channel 0 and WKUP/TIM2_ETR function in regulator ON mode.
15 PA1 bidirectional GPIO Port A pin 1 (5 V tolerant) with USART2/Timer/ADC channel 1 capability.
16 PA2 bidirectional GPIO Port A pin 2 (5 V tolerant) with USART2/Timer/ADC channel 2 capability.
17 PA3 bidirectional GPIO Port A pin 3 (5 V tolerant) with USART2/Timer/ADC channel 3 capability.
18 VSS power_in Ground reference (0 V) for digital logic; must be connected to external supply ground.
19 VDD power_in Main power supply (1.7-3.6 V); must be decoupled with ceramic capacitors placed close to device.
20 PA4 bidirectional GPIO Port A pin 4 (5 V tolerant) with SPI1/SPI3/USART2/ADC channel 4 capability.
21 PA5 bidirectional GPIO Port A pin 5 (5 V tolerant) with SPI1 clock and Timer/ADC channel 5 capability.
22 PA6 bidirectional GPIO Port A pin 6 (5 V tolerant) with SPI1 MISO and Timer/ADC channel 6 capability.
23 PA7 bidirectional GPIO Port A pin 7 (5 V tolerant) with SPI1 MOSI and Timer/ADC channel 7 capability.
24 PC4 bidirectional GPIO Port C pin 4 (5 V tolerant) with ADC1 input channel 14 capability.
25 PC5 bidirectional GPIO Port C pin 5 (5 V tolerant) with ADC1 input channel 15 capability.
26 PB0 bidirectional GPIO Port B pin 0 (5 V tolerant) with Timer/ADC channel 8 capability.
27 PB1 bidirectional GPIO Port B pin 1 (5 V tolerant) with Timer/ADC channel 9 capability.
28 PB2 bidirectional GPIO Port B pin 2 (5 V tolerant) with BOOT1 function in backup domain.
29 PB10 bidirectional GPIO Port B pin 10 (5 V tolerant) with I2C2 clock and Timer/SPI capability.
30 VCAP_1 passive Capacitor connection pin for internal voltage regulator; requires 2.2 µF ceramic capacitor with ESR < 2 Ω.
31 VSS power_in Ground reference (0 V) for digital logic; must be connected to external supply ground.
32 VDD power_in Main power supply (1.7-3.6 V); must be decoupled with ceramic capacitors placed close to device.
33 PB12 bidirectional GPIO Port B pin 12 (5 V tolerant) with SPI2/I2C2/Timer capability and SMBus alert function.
34 PB13 bidirectional GPIO Port B pin 13 (5 V tolerant) with SPI2/I2S2 clock and Timer capability.
35 PB14 bidirectional GPIO Port B pin 14 (5 V tolerant) with SPI2/I2S2 MISO and Timer capability.
36 PB15 bidirectional GPIO Port B pin 15 (5 V tolerant) with SPI2/I2S2 MOSI and Timer capability; can provide RTC reference input.
37 PC6 bidirectional GPIO Port C pin 6 (5 V tolerant) with I2S2/USART6/Timer/SDIO capability and master clock output.
38 PC7 bidirectional GPIO Port C pin 7 (5 V tolerant) with I2S3/USART6/Timer/SDIO capability and master clock output.
39 PC8 bidirectional GPIO Port C pin 8 (5 V tolerant) with USART6/Timer/SDIO data line capability.
40 PC9 bidirectional GPIO Port C pin 9 (5 V tolerant) with I2C3/Timer/SDIO/MCO2 and I2S clock input capability.
41 PA8 bidirectional GPIO Port A pin 8 (5 V tolerant) with I2C3/USART1/Timer/USB/MCO1 and debug function.
42 PA9 bidirectional GPIO Port A pin 9 (5 V tolerant) with I2C3/USART1/Timer/USB VBUS sensing capability.
43 PA10 bidirectional GPIO Port A pin 10 (5 V tolerant) with USART1/Timer/USB ID detection capability.
44 PA11 bidirectional GPIO Port A pin 11 (5 V tolerant) with USART1/Timer/USB DM (D minus) signal line.
45 PA12 bidirectional GPIO Port A pin 12 (5 V tolerant) with USART1/Timer/USB DP (D plus) signal line.
46 PA13 (JTMS-SWDIO) bidirectional GPIO Port A pin 13 or JTAG/SWD debug port pin SWDIO (5 V tolerant); used for in-circuit debug.
47 VSS power_in Ground reference (0 V) for digital logic; must be connected to external supply ground.
48 VDD power_in Main power supply (1.7-3.6 V); must be decoupled with ceramic capacitors placed close to device.
49 PA14 (JTCK-SWCLK) bidirectional GPIO Port A pin 14 or JTAG/SWD debug port pin SWCLK (5 V tolerant); used for in-circuit debug.
50 PA15 (JTDI) bidirectional GPIO Port A pin 15 or JTAG debug port pin JTDI (5 V tolerant) with SPI/Timer capability.
51 PC10 bidirectional GPIO Port C pin 10 (5 V tolerant) with SPI3/I2S3 clock and SDIO data line capability.
52 PC11 bidirectional GPIO Port C pin 11 (5 V tolerant) with SPI3/I2S3 MISO and SDIO data line capability.
53 PC12 bidirectional GPIO Port C pin 12 (5 V tolerant) with SPI3/I2S3 MOSI and SDIO clock capability.
54 PD2 bidirectional GPIO Port D pin 2 (5 V tolerant) with Timer external trigger and SDIO command line capability.
55 PB3 (JTDO-SWO) bidirectional GPIO Port B pin 3 or JTAG debug port pin JTDO/SWO (5 V tolerant) with SPI/I2C/Timer capability.
56 PB4 (NJTRST) bidirectional GPIO Port B pin 4 or JTAG debug port pin NJTRST (5 V tolerant) with SPI/I2C/Timer capability.
57 PB5 bidirectional GPIO Port B pin 5 (5 V tolerant) with SPI1/SPI3/I2C1/Timer capability.
58 PB6 bidirectional GPIO Port B pin 6 (5 V tolerant) with I2C1 clock and USART1/Timer capability.
59 PB7 bidirectional GPIO Port B pin 7 (5 V tolerant) with I2C1 data and USART1/Timer capability.
60 BOOT0 input Boot pin for selecting boot mode (0: Boot from Flash, 1: Boot from system memory); must be pulled to VSS or VDD.
61 PB8 bidirectional GPIO Port B pin 8 (5 V tolerant) with I2C1/Timer/SDIO data line capability.
62 PB9 bidirectional GPIO Port B pin 9 (5 V tolerant) with SPI2/I2S2/I2C1/Timer/SDIO data line capability.
63 VSS power_in Ground reference (0 V) for digital logic; must be connected to external supply ground.
64 VDD power_in Main power supply (1.7-3.6 V); must be decoupled with ceramic capacitors placed close to device.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32F401RBT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f401rbt6-etched.step / stm32f401rbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f401rbt6.step / stm32f401rbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (139 pp, sha256 ea0100f21bbbb0da, retrieved 2026-09-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF