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STM32F401CBU3

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f401cbu3factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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STM32F401CBU3

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)

STM32F401CBU3 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery supply voltage input, 1.7 V to 3.6 V, for RTC and backup domain.
2 PC13 bidirectional GPIO with RTC tamper input, RTC event output, and eventout capability.
3 PC14-OSC32_IN bidirectional GPIO with 32.768 kHz oscillator input function, internally connected oscillator input.
4 PC15-OSC32_OUT bidirectional GPIO with 32.768 kHz oscillator output function, internally connected oscillator output.
5 PH0-OSC_IN bidirectional GPIO with 4-26 MHz main oscillator input function.
6 PH1-OSC_OUT bidirectional GPIO with 4-26 MHz main oscillator output function.
7 NRST bidirectional Reset input with internal weak pull-up resistor and Schmitt trigger for hardware reset generation.
8 VSSA/VREF- power_in Analog ground reference, must be connected to VSS, serves as ADC reference negative input.
9 VDDA/VREF+ power_out Analog supply voltage 1.8 V to 3.6 V and ADC reference positive, requires 100 nF to 1 µF decoupling capacitor to VSSA.
10 PA0 bidirectional GPIO with ADC input channel 0, wake-up capability, and timer input/output function.
11 PA1 bidirectional GPIO with ADC input channel 1 and timer input/output capability.
12 PA2 bidirectional GPIO with ADC input channel 2, USART2 transmit, and timer input/output capability.
13 PA3 bidirectional GPIO with ADC input channel 3, USART2 receive, and timer input/output capability.
14 PA4 bidirectional GPIO with ADC input channel 4, SPI1/SPI3 chip select, and timer capability.
15 PA5 bidirectional GPIO with ADC input channel 5, SPI1 clock, and timer input/output capability.
16 PA6 bidirectional GPIO with ADC input channel 6, SPI1 MISO, TIM1 break-in, and timer input/output capability.
17 PA7 bidirectional GPIO with ADC input channel 7, SPI1 MOSI, TIM1 complementary output, and timer capability.
18 PB0 bidirectional GPIO with ADC input channel 8, TIM1 complementary output, and timer input/output capability.
19 PB1 bidirectional GPIO with ADC input channel 9, TIM1 complementary output, and timer input/output capability.
20 PB2 bidirectional GPIO with boot mode select functionality and eventout capability, labeled BOOT1 option.
21 PB10 bidirectional GPIO with I2C2 clock, SPI2 clock, and timer input/output capability.
22 VCAP_1 passive Decoupling capacitor connection for internal voltage regulator, 100 nF to 1 µF capacitor required between VCAP_1 and VCAP_2.
23 VSS power_in Ground reference voltage, must be connected to power supply ground plane.
24 VDD power_out Digital supply voltage, 1.7 V to 3.6 V operating range.
25 PB12 bidirectional GPIO with SPI2 chip select, I2C2 SMBus alert, TIM1 break-in, and timer capability.
26 PB13 bidirectional GPIO with SPI2 clock, TIM1 complementary output, and timer input/output capability.
27 PB14 bidirectional GPIO with SPI2 MISO, TIM1 complementary output, and timer input/output capability.
28 PB15 bidirectional GPIO with SPI2 MOSI, RTC reference input, TIM1 complementary output, and timer capability.
29 PA8 bidirectional GPIO with I2C3 clock, USART1 clock, TIM1 output, USB SOF output, and MCO1 capability.
30 PA9 bidirectional GPIO with I2C3 SMBus alert, USART1 transmit, TIM1 output, and USB VBUS input capability.
31 PA10 bidirectional GPIO with USART1 receive, TIM1 output, USB ID input, and timer capability.
32 PA11 bidirectional GPIO with USART1 CTS, TIM1 output, and USB DM signal line capability.
33 PA12 bidirectional GPIO with USART1 RTS, TIM1 external trigger, and USB DP signal line capability.
34 PA13 bidirectional GPIO/JTAG TMS pin shared with SWD data I/O (SWDIO) for debug interface.
35 VSS power_in Ground reference voltage, must be connected to power supply ground plane.
36 VDD power_out Digital supply voltage, 1.7 V to 3.6 V operating range.
37 PA14 bidirectional GPIO/JTAG TCK pin shared with SWD clock (SWCLK) for debug interface.
38 PA15 bidirectional GPIO/JTAG TDI pin with SPI1 chip select, SPI3 chip select, and timer input/output capability.
39 PB3 bidirectional GPIO/JTAG TDO pin shared with SWO trace output and SPI1 clock capability.
40 PB4 bidirectional GPIO/JTAG TRST pin with SPI1 MISO, I2C3 SDA, and timer input/output capability.
41 PB5 bidirectional GPIO with SPI1 MOSI, I2C1 SMBus alert, SPI3 MOSI, and timer input/output capability.
42 PB6 bidirectional GPIO with I2C1 clock, USART1 transmit, and timer input/output capability.
43 PB7 bidirectional GPIO with I2C1 data, USART1 receive, and timer input/output capability.
44 BOOT0 input Boot configuration pin sampled at reset, selects boot from flash or system memory, VPP during flash programming.
45 PB8 bidirectional GPIO with I2C1 clock, TIM4 output, TIM10 input/output, and SDIO data capability.
46 PB9 bidirectional GPIO with I2C1 data, SPI2 chip select, TIM4 output, TIM11 input/output, and SDIO data capability.
47 VSS power_in Ground reference voltage, must be connected to power supply ground plane.
48 VDD power_out Digital supply voltage, 1.7 V to 3.6 V operating range.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-48(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: STM32F401CBU3
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f401cbu3-etched.step / stm32f401cbu3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f401cbu3.step / stm32f401cbu3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (139 pp, sha256 c38f92aa9d66e8cb, retrieved 2026-10-06, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF