STM32F373VCT6

@@ -15,13 +15,13 @@ STM32F373VCT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin desc | 5 | PE6 | bidirectional | 3.3V tolerant I/O for trace data output TRACED3, wakeup input WKUP3, RTC tamper detection. | | 6 | VBAT | power_in | Backup battery supply for RTC and backup registers when VDD is absent, 1.65 to 3.6 V. | | 7 | PC13 | bidirectional | Standard 3.3V I/O for RTC functions and wakeup events, maximum output 2 MHz with 30 pF load. |-| 8 | PC14 | bidirectional | Standard 3.3V I/O for OSC32_IN low-speed oscillator input for RTC clock. |-| 9 | PC15 | bidirectional | Standard 3.3V I/O for OSC32_OUT low-speed oscillator output for RTC clock. |+| 8 | PC14-OSC32_IN | bidirectional | Standard 3.3V I/O for OSC32_IN low-speed oscillator input for RTC clock. |+| 9 | PC15-OSC32_OUT | bidirectional | Standard 3.3V I/O for OSC32_OUT low-speed oscillator output for RTC clock. | | 10 | PF9 | bidirectional | 5V tolerant I/O for timer TIM14 channel 1 output compare/PWM. | | 11 | PF10 | bidirectional | 5V tolerant I/O without alternate function. |-| 12 | PF0 | bidirectional | 5V tolerant FM+ I2C open-drain I/O for I2C2 SDA with FM+ 1 MHz capability, also OSC_IN. |-| 13 | PF1 | bidirectional | 5V tolerant FM+ I2C open-drain I/O for I2C2 SCL with FM+ 1 MHz capability, also OSC_OUT. |-| 14 | NRST | bidirectional | Bidirectional reset pin with internal weak pull-up resistor, active low, filtered by 100 ns. |+| 12 | PF0-OSC_IN | bidirectional | 5V tolerant FM+ I2C open-drain I/O for I2C2 SDA with FM+ 1 MHz capability, also OSC_IN. |+| 13 | PF1-OSC_OUT | bidirectional | 5V tolerant FM+ I2C open-drain I/O for I2C2 SCL with FM+ 1 MHz capability, also OSC_OUT. |+| 14 | NRST | input | Bidirectional reset pin with internal weak pull-up resistor, active low, filtered by 100 ns. | | 15 | PC0 | bidirectional | 3.3V tolerant ADC input pin for TIM5_CH1_ETR trigger and ADC_IN10 analog input. | | 16 | PC1 | bidirectional | 3.3V tolerant ADC input pin for TIM5_CH2 trigger and ADC_IN11 analog input. | | 17 | PC2 | bidirectional | 3.3V tolerant ADC input pin for SPI2 MISO/I2S2 MCK or TIM5_CH3, ADC_IN12 analog input. |@@ -35,7 +35,7 @@ STM32F373VCT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin desc | 25 | PA2 | bidirectional | 3.3V tolerant ADC input TSC touch sensing group 1 I/O, USART2/timer alternates, ADC_IN2. | | 26 | PA3 | bidirectional | 3.3V tolerant ADC input TSC touch sensing group 1 I/O, USART2/timer alternates, ADC_IN3. | | 27 | PF4 | bidirectional | 5V tolerant I/O without alternate function. |-| 28 | VDD_2 | power_in | Digital power supply 2.0 to 3.6 V for I/O logic. |+| 28 | VDD | power_in |  | | 29 | PA4 | bidirectional | 3.3V tolerant ADC input TSC touch sensing group 2 I/O, SPI/timer/USART alternates, DAC1_OUT1, ADC_IN4. | | 30 | PA5 | bidirectional | 3.3V tolerant ADC input TSC touch sensing group 2 I/O, SPI/timer alternates, DAC1_OUT2, ADC_IN5. | | 31 | PA6 | bidirectional | 3.3V tolerant ADC input TSC touch sensing group 2 I/O, SPI/timer alternates, DAC2_OUT1, ADC_IN6. |@@ -81,33 +81,33 @@ STM32F373VCT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin desc | 71 | PA12 | bidirectional | 5V tolerant I/O for SPI/USART/CAN/USB/timer alternates, COMP2_OUT. | | 72 | PA13 | bidirectional | 5V tolerant I/O for SPI/USART/timer/TSC/IR/JTAG alternates, SWDIO debug pin. | | 73 | PF6 | bidirectional | 5V tolerant FM+ I/O for SPI1/I2C/USART/timer alternates, 1 MHz I2C capability. |-| 74 | VSS_3 | power_in | Digital ground reference for I/O logic. |-| 75 | VDD_3 | power_in | Digital power supply 2.0 to 3.6 V for I/O logic. |-| 76 | PF7 | bidirectional | 5V tolerant FM+ I/O for I2C2/USART2 alternates, 1 MHz I2C capability. |-| 77 | PA14 | bidirectional | 5V tolerant FM+ I/O for I2C/timer/TSC/JTAG alternates, SWCLK debug pin. |-| 78 | PA15 | bidirectional | 5V tolerant FM+ I/O for SPI/I2C/timer/TSC/JTAG alternates. |-| 79 | PC10 | bidirectional | 5V tolerant I/O for SPI3/USART3/timer alternates without additional function. |-| 80 | PC11 | bidirectional | 5V tolerant I/O for SPI3/USART3/timer alternates without additional function. |-| 81 | PC12 | bidirectional | 5V tolerant I/O for SPI3/USART3/timer alternates without additional function. |-| 82 | PD0 | bidirectional | 5V tolerant I/O for CAN/timer alternates without additional function. |-| 83 | PD1 | bidirectional | 5V tolerant I/O for CAN/timer alternates without additional function. |-| 84 | PD2 | bidirectional | 5V tolerant I/O for timer external trigger alternate function. |-| 85 | PD3 | bidirectional | 5V tolerant I/O for SPI2/USART2 alternates without additional function. |-| 86 | PD4 | bidirectional | 5V tolerant I/O for SPI2/USART2 alternates without additional function. |-| 87 | PD5 | bidirectional | 5V tolerant I/O for USART2 transmit alternate function. |-| 88 | PD6 | bidirectional | 5V tolerant I/O for SPI2/USART2 alternates without additional function. |-| 89 | PD7 | bidirectional | 5V tolerant I/O for SPI2/USART2 alternates without additional function. |-| 90 | PB3 | bidirectional | 5V tolerant I/O for SPI/USART/timer/TSC/JTAG alternates, JTDO-TRACESWO output. |-| 91 | PB4 | bidirectional | 5V tolerant I/O for SPI/timer/TSC/JTAG alternates, NJTRST debug input. |-| 92 | PB5 | bidirectional | 5V tolerant I/O for SPI/I2C/USART/timer/TSC alternates without additional function. |-| 93 | PB6 | bidirectional | 5V tolerant FM+ I/O for I2C/USART/timer/TSC alternates, 1 MHz I2C capability. |-| 94 | PB7 | bidirectional | 5V tolerant FM+ I/O for I2C/USART/timer/TSC alternates, 1 MHz I2C capability. |-| 95 | BOOT0 | input | Boot mode selection pin, selects boot from flash memory, system memory, or SRAM. |-| 96 | PB8 | bidirectional | 5V tolerant FM+ I/O for SPI/I2C/USART/CAN/CEC/timer/TSC alternates, COMP1_OUT. |-| 97 | PB9 | bidirectional | 5V tolerant FM+ I/O for SPI/I2C/USART/CAN/timer alternates, COMP2_OUT. |-| 98 | PE0 | bidirectional | 5V tolerant I/O for USART1/timer alternates without additional function. |-| 99 | PE1 | bidirectional | 5V tolerant I/O for USART1 receive alternate function. |-| 100 | VSS_1 | power_in | Digital ground reference for I/O logic. |+| 74 | VSS | power_in |  |+| 75 | VDD | power_in |  |+| 76 | PA14 | bidirectional | 5V tolerant FM+ I/O for I2C/timer/TSC/JTAG alternates, SWCLK debug pin. |+| 77 | PA15 | bidirectional | 5V tolerant FM+ I/O for SPI/I2C/timer/TSC/JTAG alternates. |+| 78 | PC10 | bidirectional | 5V tolerant I/O for SPI3/USART3/timer alternates without additional function. |+| 79 | PC11 | bidirectional | 5V tolerant I/O for SPI3/USART3/timer alternates without additional function. |+| 80 | PC12 | bidirectional | 5V tolerant I/O for SPI3/USART3/timer alternates without additional function. |+| 81 | PD0 | bidirectional | 5V tolerant I/O for CAN/timer alternates without additional function. |+| 82 | PD1 | bidirectional | 5V tolerant I/O for CAN/timer alternates without additional function. |+| 83 | PD2 | bidirectional | 5V tolerant I/O for timer external trigger alternate function. |+| 84 | PD3 | bidirectional | 5V tolerant I/O for SPI2/USART2 alternates without additional function. |+| 85 | PD4 | bidirectional | 5V tolerant I/O for SPI2/USART2 alternates without additional function. |+| 86 | PD5 | bidirectional | 5V tolerant I/O for USART2 transmit alternate function. |+| 87 | PD6 | bidirectional | 5V tolerant I/O for SPI2/USART2 alternates without additional function. |+| 88 | PD7 | bidirectional | 5V tolerant I/O for SPI2/USART2 alternates without additional function. |+| 89 | PB3 | bidirectional | 5V tolerant I/O for SPI/USART/timer/TSC/JTAG alternates, JTDO-TRACESWO output. |+| 90 | PB4 | bidirectional | 5V tolerant I/O for SPI/timer/TSC/JTAG alternates, NJTRST debug input. |+| 91 | PB5 | bidirectional | 5V tolerant I/O for SPI/I2C/USART/timer/TSC alternates without additional function. |+| 92 | PB6 | bidirectional | 5V tolerant FM+ I/O for I2C/USART/timer/TSC alternates, 1 MHz I2C capability. |+| 93 | PB7 | bidirectional | 5V tolerant FM+ I/O for I2C/USART/timer/TSC alternates, 1 MHz I2C capability. |+| 94 | BOOT0 | input | Boot mode selection pin, selects boot from flash memory, system memory, or SRAM. |+| 95 | PB8 | bidirectional | 5V tolerant FM+ I/O for SPI/I2C/USART/CAN/CEC/timer/TSC alternates, COMP1_OUT. |+| 96 | PB9 | bidirectional | 5V tolerant FM+ I/O for SPI/I2C/USART/CAN/timer alternates, COMP2_OUT. |+| 97 | PE0 | bidirectional | 5V tolerant I/O for USART1/timer alternates without additional function. |+| 98 | PE1 | bidirectional | 5V tolerant I/O for USART1 receive alternate function. |+| 99 | VSS | power_in |  |+| 100 | VDD | power_in |  |  ## Key specifications 

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@@ -50,7 +50,7 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description></description>+<description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST&apos;s open pin data</description> <packages> <package name="LQFP-100_14x14mm_P0.5mm">   <description>LQFP-100, 14 x 14 mm, 0.5 mm pitch</description>@@ -180,6 +180,7 @@ </packages> <symbols> <symbol name="STM32F373VCT6">+  <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST&apos;s open pin data</description>   <wire x1="-12.7" y1="63.5" x2="12.7" y2="63.5" width="0.254" layer="94"/>   <wire x1="12.7" y1="63.5" x2="12.7" y2="-66.04" width="0.254" layer="94"/>   <wire x1="12.7" y1="-66.04" x2="-12.7" y2="-66.04" width="0.254" layer="94"/>@@ -193,13 +194,13 @@   <pin name="PE6" x="-17.78" y="50.8" length="middle" direction="io"/>   <pin name="VBAT" x="-17.78" y="48.26" length="middle" direction="pwr"/>   <pin name="PC13" x="-17.78" y="45.72" length="middle" direction="io"/>-  <pin name="PC14" x="-17.78" y="43.18" length="middle" direction="io"/>-  <pin name="PC15" x="-17.78" y="40.64" length="middle" direction="io"/>+  <pin name="PC14-OSC32_IN" x="-17.78" y="43.18" length="middle" direction="io"/>+  <pin name="PC15-OSC32_OUT" x="-17.78" y="40.64" length="middle" direction="io"/>   <pin name="PF9" x="-17.78" y="38.1" length="middle" direction="io"/>   <pin name="PF10" x="-17.78" y="35.56" length="middle" direction="io"/>-  <pin name="PF0" x="-17.78" y="33.02" length="middle" direction="io"/>-  <pin name="PF1" x="-17.78" y="30.48" length="middle" direction="io"/>-  <pin name="NRST" x="-17.78" y="27.94" length="middle" direction="io"/>+  <pin name="PF0-OSC_IN" x="-17.78" y="33.02" length="middle" direction="io"/>+  <pin name="PF1-OSC_OUT" x="-17.78" y="30.48" length="middle" direction="io"/>+  <pin name="NRST" x="-17.78" y="27.94" length="middle" direction="in"/>   <pin name="PC0" x="-17.78" y="25.4" length="middle" direction="io"/>   <pin name="PC1" x="-17.78" y="22.86" length="middle" direction="io"/>   <pin name="PC2" x="-17.78" y="20.32" length="middle" direction="io"/>@@ -213,7 +214,7 @@   <pin name="PA2" x="-17.78" y="0" length="middle" direction="io"/>   <pin name="PA3" x="-17.78" y="-2.54" length="middle" direction="io"/>   <pin name="PF4" x="-17.78" y="-5.08" length="middle" direction="io"/>-  <pin name="VDD_2" x="-17.78" y="-7.62" length="middle" direction="pwr"/>+  <pin name="VDD" x="-17.78" y="-7.62" length="middle" direction="pwr"/>   <pin name="PA4" x="-17.78" y="-10.16" length="middle" direction="io"/>   <pin name="PA5" x="-17.78" y="-12.7" length="middle" direction="io"/>   <pin name="PA6" x="-17.78" y="-15.24" length="middle" direction="io"/>@@ -236,33 +237,33 @@   <pin name="VREFSD-" x="-17.78" y="-58.42" length="middle" direction="pwr"/>   <pin name="VSSSD" x="-17.78" y="-60.96" length="middle" direction="pwr"/>   <pin name="VDDSD12" x="-17.78" y="-63.5" length="middle" direction="pwr"/>-  <pin name="VSS_1" x="17.78" y="60.96" length="middle" direction="pwr" rot="R180"/>-  <pin name="PE1" x="17.78" y="58.42" length="middle" direction="io" rot="R180"/>-  <pin name="PE0" x="17.78" y="55.88" length="middle" direction="io" rot="R180"/>-  <pin name="PB9" x="17.78" y="53.34" length="middle" direction="io" rot="R180"/>-  <pin name="PB8" x="17.78" y="50.8" length="middle" direction="io" rot="R180"/>-  <pin name="BOOT0" x="17.78" y="48.26" length="middle" direction="in" rot="R180"/>-  <pin name="PB7" x="17.78" y="45.72" length="middle" direction="io" rot="R180"/>-  <pin name="PB6" x="17.78" y="43.18" length="middle" direction="io" rot="R180"/>-  <pin name="PB5" x="17.78" y="40.64" length="middle" direction="io" rot="R180"/>-  <pin name="PB4" x="17.78" y="38.1" length="middle" direction="io" rot="R180"/>-  <pin name="PB3" x="17.78" y="35.56" length="middle" direction="io" rot="R180"/>-  <pin name="PD7" x="17.78" y="33.02" length="middle" direction="io" rot="R180"/>-  <pin name="PD6" x="17.78" y="30.48" length="middle" direction="io" rot="R180"/>-  <pin name="PD5" x="17.78" y="27.94" length="middle" direction="io" rot="R180"/>-  <pin name="PD4" x="17.78" y="25.4" length="middle" direction="io" rot="R180"/>-  <pin name="PD3" x="17.78" y="22.86" length="middle" direction="io" rot="R180"/>-  <pin name="PD2" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/>-  <pin name="PD1" x="17.78" y="17.78" length="middle" direction="io" rot="R180"/>-  <pin name="PD0" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>-  <pin name="PC12" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>-  <pin name="PC11" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>-  <pin name="PC10" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>-  <pin name="PA15" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>-  <pin name="PA14" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>-  <pin name="PF7" x="17.78" y="0" length="middle" direction="io" rot="R180"/>-  <pin name="VDD_3" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>-  <pin name="VSS_3" x="17.78" y="-5.08" length="middle" direction="pwr" rot="R180"/>+  <pin name="VDD@2" x="17.78" y="60.96" length="middle" direction="pwr" rot="R180"/>+  <pin name="VSS" x="17.78" y="58.42" length="middle" direction="pwr" rot="R180"/>+  <pin name="PE1" x="17.78" y="55.88" length="middle" direction="io" rot="R180"/>+  <pin name="PE0" x="17.78" y="53.34" length="middle" direction="io" rot="R180"/>+  <pin name="PB9" x="17.78" y="50.8" length="middle" direction="io" rot="R180"/>+  <pin name="PB8" x="17.78" y="48.26" length="middle" direction="io" rot="R180"/>+  <pin name="BOOT0" x="17.78" y="45.72" length="middle" direction="in" rot="R180"/>+  <pin name="PB7" x="17.78" y="43.18" length="middle" direction="io" rot="R180"/>+  <pin name="PB6" x="17.78" y="40.64" length="middle" direction="io" rot="R180"/>+  <pin name="PB5" x="17.78" y="38.1" length="middle" direction="io" rot="R180"/>+  <pin name="PB4" x="17.78" y="35.56" length="middle" direction="io" rot="R180"/>+  <pin name="PB3" x="17.78" y="33.02" length="middle" direction="io" rot="R180"/>+  <pin name="PD7" x="17.78" y="30.48" length="middle" direction="io" rot="R180"/>+  <pin name="PD6" x="17.78" y="27.94" length="middle" direction="io" rot="R180"/>+  <pin name="PD5" x="17.78" y="25.4" length="middle" direction="io" rot="R180"/>+  <pin name="PD4" x="17.78" y="22.86" length="middle" direction="io" rot="R180"/>+  <pin name="PD3" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/>+  <pin name="PD2" x="17.78" y="17.78" length="middle" direction="io" rot="R180"/>+  <pin name="PD1" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>+  <pin name="PD0" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>+  <pin name="PC12" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>+  <pin name="PC11" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>+  <pin name="PC10" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+  <pin name="PA15" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+  <pin name="PA14" x="17.78" y="0" length="middle" direction="io" rot="R180"/>+  <pin name="VDD@3" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>+  <pin name="VSS@2" x="17.78" y="-5.08" length="middle" direction="pwr" rot="R180"/>   <pin name="PF6" x="17.78" y="-7.62" length="middle" direction="io" rot="R180"/>   <pin name="PA13" x="17.78" y="-10.16" length="middle" direction="io" rot="R180"/>   <pin name="PA12" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>@@ -290,7 +291,7 @@ </symbols> <devicesets> <deviceset name="STM32F373VCT6" prefix="U">-  <description></description>+  <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST&apos;s open pin data</description>   <gates>     <gate name="G$1" symbol="STM32F373VCT6" x="0" y="0"/>   </gates>@@ -304,12 +305,12 @@         <connect gate="G$1" pin="PE6" pad="5"/>         <connect gate="G$1" pin="VBAT" pad="6"/>         <connect gate="G$1" pin="PC13" pad="7"/>-        <connect gate="G$1" pin="PC14" pad="8"/>-        <connect gate="G$1" pin="PC15" pad="9"/>+        <connect gate="G$1" pin="PC14-OSC32_IN" pad="8"/>+        <connect gate="G$1" pin="PC15-OSC32_OUT" pad="9"/>         <connect gate="G$1" pin="PF9" pad="10"/>         <connect gate="G$1" pin="PF10" pad="11"/>-        <connect gate="G$1" pin="PF0" pad="12"/>-        <connect gate="G$1" pin="PF1" pad="13"/>+        <connect gate="G$1" pin="PF0-OSC_IN" pad="12"/>+        <connect gate="G$1" pin="PF1-OSC_OUT" pad="13"/>         <connect gate="G$1" pin="NRST" pad="14"/>         <connect gate="G$1" pin="PC0" pad="15"/>         <connect gate="G$1" pin="PC1" pad="16"/>@@ -324,7 +325,7 @@         <connect gate="G$1" pin="PA2" pad="25"/>         <connect gate="G$1" pin="PA3" pad="26"/>         <connect gate="G$1" pin="PF4" pad="27"/>-        <connect gate="G$1" pin="VDD_2" pad="28"/>+        <connect gate="G$1" pin="VDD" pad="28"/>         <connect gate="G$1" pin="PA4" pad="29"/>         <connect gate="G$1" pin="PA5" pad="30"/>         <connect gate="G$1" pin="PA6" pad="31"/>@@ -347,33 +348,33 @@         <connect gate="G$1" pin="VREFSD-" pad="48"/>         <connect gate="G$1" pin="VSSSD" pad="49"/>         <connect gate="G$1" pin="VDDSD12" pad="50"/>-        <connect gate="G$1" pin="VSS_1" pad="100"/>-        <connect gate="G$1" pin="PE1" pad="99"/>-        <connect gate="G$1" pin="PE0" pad="98"/>-        <connect gate="G$1" pin="PB9" pad="97"/>-        <connect gate="G$1" pin="PB8" pad="96"/>-        <connect gate="G$1" pin="BOOT0" pad="95"/>-        <connect gate="G$1" pin="PB7" pad="94"/>-        <connect gate="G$1" pin="PB6" pad="93"/>-        <connect gate="G$1" pin="PB5" pad="92"/>-        <connect gate="G$1" pin="PB4" pad="91"/>-        <connect gate="G$1" pin="PB3" pad="90"/>-        <connect gate="G$1" pin="PD7" pad="89"/>-        <connect gate="G$1" pin="PD6" pad="88"/>-        <connect gate="G$1" pin="PD5" pad="87"/>-        <connect gate="G$1" pin="PD4" pad="86"/>-        <connect gate="G$1" pin="PD3" pad="85"/>-        <connect gate="G$1" pin="PD2" pad="84"/>-        <connect gate="G$1" pin="PD1" pad="83"/>-        <connect gate="G$1" pin="PD0" pad="82"/>-        <connect gate="G$1" pin="PC12" pad="81"/>-        <connect gate="G$1" pin="PC11" pad="80"/>-        <connect gate="G$1" pin="PC10" pad="79"/>-        <connect gate="G$1" pin="PA15" pad="78"/>-        <connect gate="G$1" pin="PA14" pad="77"/>-        <connect gate="G$1" pin="PF7" pad="76"/>-        <connect gate="G$1" pin="VDD_3" pad="75"/>-        <connect gate="G$1" pin="VSS_3" pad="74"/>+        <connect gate="G$1" pin="VDD@2" pad="100"/>+        <connect gate="G$1" pin="VSS" pad="99"/>+        <connect gate="G$1" pin="PE1" pad="98"/>+        <connect gate="G$1" pin="PE0" pad="97"/>+        <connect gate="G$1" pin="PB9" pad="96"/>+        <connect gate="G$1" pin="PB8" pad="95"/>+        <connect gate="G$1" pin="BOOT0" pad="94"/>+        <connect gate="G$1" pin="PB7" pad="93"/>+        <connect gate="G$1" pin="PB6" pad="92"/>+        <connect gate="G$1" pin="PB5" pad="91"/>+        <connect gate="G$1" pin="PB4" pad="90"/>+        <connect gate="G$1" pin="PB3" pad="89"/>+        <connect gate="G$1" pin="PD7" pad="88"/>+        <connect gate="G$1" pin="PD6" pad="87"/>+        <connect gate="G$1" pin="PD5" pad="86"/>+        <connect gate="G$1" pin="PD4" pad="85"/>+        <connect gate="G$1" pin="PD3" pad="84"/>+        <connect gate="G$1" pin="PD2" pad="83"/>+        <connect gate="G$1" pin="PD1" pad="82"/>+        <connect gate="G$1" pin="PD0" pad="81"/>+        <connect gate="G$1" pin="PC12" pad="80"/>+        <connect gate="G$1" pin="PC11" pad="79"/>+        <connect gate="G$1" pin="PC10" pad="78"/>+        <connect gate="G$1" pin="PA15" pad="77"/>+        <connect gate="G$1" pin="PA14" pad="76"/>+        <connect gate="G$1" pin="VDD@3" pad="75"/>+        <connect gate="G$1" pin="VSS@2" pad="74"/>         <connect gate="G$1" pin="PF6" pad="73"/>         <connect gate="G$1" pin="PA13" pad="72"/>         <connect gate="G$1" pin="PA12" pad="71"/>@@ -398,7 +399,17 @@         <connect gate="G$1" pin="VREFSD+" pad="52"/>         <connect gate="G$1" pin="VDDSD3" pad="51"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="STM32F373VCT6" constant="no"/>+          <attribute name="MANUFACTURER" value="STMicroelectronics" constant="no"/>+          <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893258982297600" constant="no"/>+          <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/stm32f373vct6" constant="no"/>+          <attribute name="MOUSER_PN" value="511-STM32F373VCT6" constant="no"/>+          <attribute name="DIGIKEY_PN" value="497-13234-ND" constant="no"/>+          <attribute name="LCSC_PN" value="C1121903" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>