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STM32F358VCT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F358VCT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F358VCT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V tolerant (FT) I/O; alternate functions TRACECK, TIM3_CH1, TSC_G7_IO1, EVENTOUT.
2 PE3 bidirectional 5 V tolerant (FT) I/O; alternate functions TRACED0, TIM3_CH2, TSC_G7_IO2, EVENTOUT.
3 PE4 bidirectional 5 V tolerant (FT) I/O; alternate functions TRACED1, TIM3_CH3, TSC_G7_IO3, EVENTOUT.
4 PE5 bidirectional 5 V tolerant (FT) I/O; alternate functions TRACED2, TIM3_CH4, TSC_G7_IO4, EVENTOUT.
5 PE6 bidirectional 5 V tolerant (FT) I/O; alternate functions TRACED3, EVENTOUT; additional functions WKUP3, RTC_TAMP3.
6 VBAT power_in Backup power supply for RTC and backup registers.
7 PC13 bidirectional Standard 3.3 V (TC) I/O supplied through the power switch (3 mA max sink, output speed max 2 MHz with 30 pF load, not a current source); TIM1_CH1N, WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT.
8 PC14-OSC32_IN bidirectional Standard 3.3 V (TC) I/O supplied through the power switch (limited output use per note 2) that also serves as the OSC32_IN 32 kHz oscillator input.
9 PC15-OSC32_OUT bidirectional Standard 3.3 V (TC) I/O supplied through the power switch (limited output use per note 2) that also serves as the OSC32_OUT 32 kHz oscillator output.
10 PF9 bidirectional 5 V tolerant (FT) I/O; alternate functions TIM15_CH1, SPI2_SCK, EVENTOUT.
11 PF10 bidirectional 5 V tolerant (FT) I/O; alternate functions TIM15_CH2, SPI2_SCK, EVENTOUT.
12 PF0-OSC_IN bidirectional 5 V tolerant FM+ capable (FTf) I/O; TIM1_CH3N, I2C2_SDA, and OSC_IN main oscillator input.
13 PF1-OSC_OUT bidirectional 5 V tolerant FM+ capable (FTf) I/O; I2C2_SCL, and OSC_OUT main oscillator output.
14 NRST bidirectional Device reset input / internal reset output (active low), bidirectional reset pin with embedded weak pull-up resistor.
15 PC0 bidirectional 3.3 V tolerant I/O directly connected to ADC (TTa); EVENTOUT, ADC12_IN6, COMP7_INM.
16 PC1 bidirectional TTa I/O; EVENTOUT, ADC12_IN7, COMP7_INP.
17 PC2 bidirectional TTa I/O; COMP7_OUT, EVENTOUT, ADC12_IN8.
18 PC3 bidirectional TTa I/O; TIM1_BKIN2, EVENTOUT, ADC12_IN9.
19 PF2 bidirectional TTa I/O; EVENTOUT, ADC12_IN10.
20 VSSA/VREF- power_in Analog ground / negative reference voltage.
21 VREF+ power_in Positive reference voltage (ADC VREF+ range 2 V to VDDA).
22 VDDA power_in Analog power supply (VDDA range 1.65 to 3.6 V).
23 PA0 bidirectional TTa I/O; USART2_CTS, TIM2_CH1_ETR, TIM8_BKIN, TIM8_ETR, TSC_G1_IO1, COMP1_OUT, ADC1_IN1, COMP1_INM, RTC_TAMP2, WKUP1, COMP7_INP.
24 PA1 bidirectional TTa I/O; USART2_RTS_DE, TIM2_CH2, TSC_G1_IO2, TIM15_CH1N, RTC_REFIN, ADC1_IN2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP.
25 PA2 bidirectional TTa I/O (reduced touch sensitivity); USART2_TX, TIM2_CH3, TIM15_CH1, TSC_G1_IO3, COMP2_OUT, ADC1_IN3, COMP2_INM, OPAMP1_VOUT.
26 PA3 bidirectional TTa I/O; USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4, ADC1_IN4, OPAMP1_VINP, COMP2_INP, OPAMP1_VINM.
27 PF4 bidirectional TTa I/O; COMP1_OUT, EVENTOUT, ADC1_IN5.
28 VDD_4 power_in Digital power supply.
29 PA4 bidirectional TTa I/O (reduced touch sensitivity); SPI1_NSS, SPI3_NSS, I2S3_WS, USART2_CK, TSC_G2_IO1, TIM3_CH2, ADC2_IN1, DAC1_OUT1, OPAMP4_VINP, COMP1-7_INM.
30 PA5 bidirectional TTa I/O (reduced touch sensitivity); SPI1_SCK, TIM2_CH1_ETR, TSC_G2_IO2, ADC2_IN2, DAC1_OUT2, OPAMP1/2/3 inputs, COMP1-7_INM.
31 PA6 bidirectional TTa I/O (reduced touch sensitivity); SPI1_MISO, TIM3_CH1, TIM8_BKIN, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, ADC2_IN3, OPAMP2_VOUT.
32 PA7 bidirectional TTa I/O; SPI1_MOSI, TIM3_CH2, TIM17_CH1, TIM1_CH1N, TIM8_CH1N, TSC_G2_IO4, COMP2_OUT, ADC2_IN4, COMP2_INP, OPAMP2_VINP, OPAMP1_VINP.
33 PC4 bidirectional TTa I/O; USART1_TX, EVENTOUT, ADC2_IN5.
34 PC5 bidirectional TTa I/O; USART1_RX, TSC_G3_IO1, EVENTOUT, ADC2_IN11, OPAMP2_VINM, OPAMP1_VINM.
35 PB0 bidirectional TTa I/O; TIM3_CH3, TIM1_CH2N, TIM8_CH2N, TSC_G3_IO2, ADC3_IN12, COMP4_INP, OPAMP3_VINP, OPAMP2_VINP.
36 PB1 bidirectional TTa I/O (reduced touch sensitivity); TIM3_CH4, TIM1_CH3N, TIM8_CH3N, COMP4_OUT, TSC_G3_IO3, ADC3_IN1, OPAMP3_VOUT.
37 NPOR input Device power-on reset input, external POR pin with embedded weak pull-up resistor, powered by VDDA.
38 PE7 bidirectional TTa I/O; TIM1_ETR, EVENTOUT, ADC3_IN13, COMP4_INP.
39 PE8 bidirectional TTa I/O; TIM1_CH1N, EVENTOUT, COMP4_INM, ADC34_IN6.
40 PE9 bidirectional TTa I/O; TIM1_CH1, EVENTOUT, ADC3_IN2.
41 PE10 bidirectional TTa I/O; TIM1_CH2N, EVENTOUT, ADC3_IN14.
42 PE11 bidirectional TTa I/O; TIM1_CH2, EVENTOUT, ADC3_IN15.
43 PE12 bidirectional TTa I/O; TIM1_CH3N, EVENTOUT, ADC3_IN16.
44 PE13 bidirectional TTa I/O; TIM1_CH3, EVENTOUT, ADC3_IN3.
45 PE14 bidirectional TTa I/O; TIM1_CH4, TIM1_BKIN2, EVENTOUT, ADC4_IN1.
46 PE15 bidirectional TTa I/O; USART3_RX, TIM1_BKIN, EVENTOUT, ADC4_IN2.
47 PB10 bidirectional TTa I/O; USART3_TX, TIM2_CH3, TSC_SYNC, EVENTOUT, COMP5_INM, OPAMP4_VINM, OPAMP3_VINM.
48 PB11 bidirectional TTa I/O; USART3_RX, TIM2_CH4, TSC_G6_IO1, EVENTOUT, COMP6_INP, OPAMP4_VINP.
49 VSS_2 power_in Digital ground.
50 VDD_2 power_in Digital power supply.
51 PB12 bidirectional TTa I/O (reduced touch sensitivity); SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, TSC_G6_IO2, ADC4_IN3, COMP3_INM, OPAMP4_VOUT.
52 PB13 bidirectional TTa I/O; SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, TSC_G6_IO3, ADC3_IN5, COMP5_INP, OPAMP4_VINP, OPAMP3_VINP.
53 PB14 bidirectional TTa I/O; SPI2_MISO, I2S2ext_SD, USART3_RTS_DE, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4, COMP3_INP, ADC4_IN4, OPAMP2_VINP.
54 PB15 bidirectional TTa I/O; SPI2_MOSI, I2S2_SD, TIM1_CH3N, RTC_REFIN, TIM15_CH1N, TIM15_CH2, ADC4_IN5, COMP6_INM.
55 PD8 bidirectional TTa I/O; USART3_TX, EVENTOUT, ADC4_IN12, OPAMP4_VINM.
56 PD9 bidirectional TTa I/O; USART3_RX, EVENTOUT, ADC4_IN13.
57 PD10 bidirectional TTa I/O; USART3_CK, EVENTOUT, ADC34_IN7, COMP6_INM.
58 PD11 bidirectional TTa I/O; USART3_CTS, EVENTOUT, ADC34_IN8, COMP6_INP, OPAMP4_VINP.
59 PD12 bidirectional TTa I/O; USART3_RTS_DE, TIM4_CH1, TSC_G8_IO1, EVENTOUT, ADC34_IN9, COMP5_INP.
60 PD13 bidirectional TTa I/O; TIM4_CH2, TSC_G8_IO2, EVENTOUT, ADC34_IN10, COMP5_INM.
61 PD14 bidirectional TTa I/O; TIM4_CH3, TSC_G8_IO3, EVENTOUT, COMP3_INP, ADC34_IN11, OPAMP2_VINP.
62 PD15 bidirectional TTa I/O; SPI2_NSS, TIM4_CH4, TSC_G8_IO4, EVENTOUT, COMP3_INM.
63 PC6 bidirectional 5 V tolerant (FT) I/O; I2S2_MCK, COMP6_OUT, TIM8_CH1, TIM3_CH1, EVENTOUT.
64 PC7 bidirectional 5 V tolerant (FT) I/O; I2S3_MCK, TIM8_CH2, TIM3_CH2, COMP5_OUT, EVENTOUT.
65 PC8 bidirectional 5 V tolerant (FT) I/O; TIM8_CH3, TIM3_CH3, COMP3_OUT, EVENTOUT.
66 PC9 bidirectional 5 V tolerant (FT) I/O; TIM8_CH4, TIM8_BKIN2, TIM3_CH4, I2S_CKIN, EVENTOUT.
67 PA8 bidirectional 5 V tolerant (FT) I/O; I2C2_SMBA, I2S2_MCK, USART1_CK, TIM1_CH1, TIM4_ETR, MCO, COMP3_OUT, EVENTOUT.
68 PA9 bidirectional 5 V tolerant FM+ capable (FTf) I/O; I2C2_SCL, I2S3_MCK, USART1_TX, TIM1_CH2, TIM2_CH3, TIM15_BKIN, TSC_G4_IO1, COMP5_OUT, EVENTOUT.
69 PA10 bidirectional 5 V tolerant FM+ capable (FTf) I/O; I2C2_SDA, USART1_RX, TIM1_CH3, TIM2_CH4, TIM8_BKIN, TIM17_BKIN, TSC_G4_IO2, COMP6_OUT, EVENTOUT.
70 PA11 bidirectional 5 V tolerant (FT) I/O; USART1_CTS, CAN_RX, TIM1_CH1N, TIM1_CH4, TIM1_BKIN2, TIM4_CH1, COMP1_OUT, EVENTOUT.
71 PA12 bidirectional 5 V tolerant (FT) I/O; USART1_RTS_DE, CAN_TX, TIM1_CH2N, TIM1_ETR, TIM4_CH2, TIM16_CH1, COMP2_OUT, EVENTOUT.
72 PA13 bidirectional 5 V tolerant (FT) I/O; SWDIO-JTMS debug function after reset, USART3_CTS, TIM4_CH3, TIM16_CH1N, TSC_G4_IO3, IR_OUT, EVENTOUT.
73 PF6 bidirectional 5 V tolerant FM+ capable (FTf) I/O; I2C2_SCL, USART3_RTS_DE, TIM4_CH4, EVENTOUT.
74 VSS_3 power_in Ground.
75 VDD_3 power_in Digital power supply.
76 PA14 bidirectional 5 V tolerant FM+ capable (FTf) I/O; SWCLK-JTCK debug function after reset, I2C1_SDA, USART2_TX, TIM8_CH2, TIM1_BKIN, TSC_G4_IO4, EVENTOUT.
77 PA15 bidirectional 5 V tolerant FM+ capable (FTf) I/O; JTDI, I2C1_SCL, SPI1_NSS, SPI3_NSS, I2S3_WS, USART2_RX, TIM1_BKIN, TIM2_CH1_ETR, TIM8_CH1, EVENTOUT.
78 PC10 bidirectional 5 V tolerant (FT) I/O; SPI3_SCK, I2S3_CK, USART3_TX, UART4_TX, TIM8_CH1N, EVENTOUT.
79 PC11 bidirectional 5 V tolerant (FT) I/O; SPI3_MISO, I2S3ext_SD, USART3_RX, UART4_RX, TIM8_CH2N, EVENTOUT.
80 PC12 bidirectional 5 V tolerant (FT) I/O; SPI3_MOSI, I2S3_SD, USART3_CK, UART5_TX, TIM8_CH3N, EVENTOUT.
81 PD0 bidirectional 5 V tolerant (FT) I/O; CAN_RX, EVENTOUT.
82 PD1 bidirectional 5 V tolerant (FT) I/O; CAN_TX, TIM8_CH4, TIM8_BKIN2, EVENTOUT.
83 PD2 bidirectional 5 V tolerant (FT) I/O; UART5_RX, TIM3_ETR, TIM8_BKIN, EVENTOUT.
84 PD3 bidirectional 5 V tolerant (FT) I/O; USART2_CTS, TIM2_CH1_ETR, EVENTOUT.
85 PD4 bidirectional 5 V tolerant (FT) I/O; USART2_RTS_DE, TIM2_CH2, EVENTOUT.
86 PD5 bidirectional 5 V tolerant (FT) I/O; USART2_TX, EVENTOUT.
87 PD6 bidirectional 5 V tolerant (FT) I/O; USART2_RX, TIM2_CH4, EVENTOUT.
88 PD7 bidirectional 5 V tolerant (FT) I/O; USART2_CK, TIM2_CH3, EVENTOUT.
89 PB3 bidirectional 5 V tolerant (FT) I/O; JTDO-TRACESWO debug function after reset, SPI3_SCK, I2S3_CK, SPI1_SCK, USART2_TX, TIM2_CH2, TIM3_ETR, TIM4_ETR, TIM8_CH1N, TSC_G5_IO1, EVENTOUT.
90 PB4 bidirectional 5 V tolerant (FT) I/O; NJTRST debug function after reset, SPI3_MISO, I2S3ext_SD, SPI1_MISO, USART2_RX, TIM3_CH1, TIM16_CH1, TIM17_BKIN, TIM8_CH2N, TSC_G5_IO2, EVENTOUT.
91 PB5 bidirectional 5 V tolerant (FT) I/O; SPI3_MOSI, SPI1_MOSI, I2S3_SD, I2C1_SMBA, USART2_CK, TIM16_BKIN, TIM3_CH2, TIM8_CH3N, TIM17_CH1, EVENTOUT.
92 PB6 bidirectional 5 V tolerant FM+ capable (FTf) I/O; I2C1_SCL, USART1_TX, TIM16_CH1N, TIM4_CH1, TIM8_CH1, TSC_G5_IO3, TIM8_ETR, TIM8_BKIN2, EVENTOUT.
93 PB7 bidirectional 5 V tolerant FM+ capable (FTf) I/O; I2C1_SDA, USART1_RX, TIM3_CH4, TIM4_CH2, TIM17_CH1N, TIM8_BKIN, TSC_G5_IO4, EVENTOUT.
94 BOOT0 input Dedicated boot memory selection input.
95 PB8 bidirectional 5 V tolerant FM+ capable (FTf) I/O; I2C1_SCL, CAN_RX, TIM16_CH1, TIM4_CH3, TIM8_CH2, TIM1_BKIN, TSC_SYNC, COMP1_OUT, EVENTOUT.
96 PB9 bidirectional 5 V tolerant FM+ capable (FTf) I/O; I2C1_SDA, CAN_TX, TIM17_CH1, TIM4_CH4, TIM8_CH3, IR_OUT, COMP2_OUT, EVENTOUT.
97 PE0 bidirectional 5 V tolerant (FT) I/O; USART1_TX, TIM4_ETR, TIM16_CH1, EVENTOUT.
98 PE1 bidirectional 5 V tolerant (FT) I/O; USART1_RX, TIM17_CH1, EVENTOUT.
99 VSS_1 power_in Ground.
100 VDD_1 power_in Digital power supply.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F358VCT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f358vct6-etched.step / stm32f358vct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f358vct6.step / stm32f358vct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (134 pp, sha256 a43070cb13b2b195, retrieved 2026-10-03, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF