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STM32F303K8T6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F303K8T6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
STM32F303K8T6 from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Main digital power supply, 2.0 to 3.6 V; decoupling capacitors (100 nF ceramic + 1 µF) required as close as possible to pin. |
| 2 | PF0/OSC_IN | bidirectional | 5 V-tolerant (FT) GPIO port F bit 0; AF6: TIM1_CH3N; additional function OSC_IN for HSE crystal oscillator (4-32 MHz); reset state: floating input. |
| 3 | PF1/OSC_OUT | bidirectional | 5 V-tolerant (FT) GPIO port F bit 1; additional function OSC_OUT for HSE crystal oscillator; reset state: floating input. |
| 4 | NRST | bidirectional | Bidirectional reset pin (RST type) with embedded weak pull-up resistor (25-55 kΩ typical 40 kΩ); active-low device reset input / internal reset output; filters pulses shorter than 100 ns. |
| 5 | VDDA/VREF+ | power_in | Analog power supply and ADC/DAC positive reference voltage, 2.0 to 3.6 V (minimum 2.4 V when OPAMP or DAC are used); must be ≥ VDD and must power on before or simultaneously with VDD. |
| 6 | PA0 | bidirectional | 3.3 V TTa GPIO PA0; AF: TIM2_CH1/TIM2_ETR, TSC_G1_IO1, USART2_CTS, EVENTOUT; additional: ADC1_IN1 (fast channel), RTC_TAMP2/WKUP1; reset state: floating input. |
| 7 | PA1 | bidirectional | 3.3 V TTa GPIO PA1; AF: TIM2_CH2, TSC_G1_IO2, USART2_RTS_DE, TIM15_CH1N, EVENTOUT; additional: ADC1_IN2 (fast channel), RTC_REFIN; reset state: floating input. |
| 8 | PA2 | bidirectional | 3.3 V TTa GPIO PA2; AF: TIM2_CH3, TSC_G1_IO3, USART2_TX, COMP2_OUT, TIM15_CH1, EVENTOUT; additional: ADC1_IN3 (fast channel), COMP2_INM; reset state: floating input. |
| 9 | PA3 | bidirectional | 3.3 V TTa GPIO PA3; AF: TIM2_CH4, TSC_G1_IO4, USART2_RX, TIM15_CH2, EVENTOUT; additional: ADC1_IN4 (fast channel); reset state: floating input. |
| 10 | PA4 | bidirectional | 3.3 V TTa GPIO PA4 (reduced TSC sensitivity; recommended as sampling-capacitor I/O); AF: TIM3_CH2, TSC_G2_IO1, SPI1_NSS, USART2_CK, EVENTOUT; additional: ADC2_IN1 (fast channel), DAC1_OUT1, COMP2/4/6_INM4. |
| 11 | PA5 | bidirectional | 3.3 V TTa GPIO PA5 (reduced TSC sensitivity; recommended as sampling-capacitor I/O); AF: TIM2_CH1/TIM2_ETR, TSC_G2_IO2, SPI1_SCK, EVENTOUT; additional: ADC2_IN2 (fast channel), DAC1_OUT2, OPAMP2_VINM. |
| 12 | PA6 | bidirectional | 3.3 V TTa GPIO PA6 (reduced TSC sensitivity; recommended as sampling-capacitor I/O); AF: TIM16_CH1, TIM3_CH1, TSC_G2_IO3, SPI1_MISO, TIM1_BKIN, EVENTOUT; additional: ADC2_IN3 (slow channel), DAC2_OUT1, OPAMP2_VOUT. |
| 13 | PA7 | bidirectional | 3.3 V TTa GPIO PA7; AF: TIM17_CH1, TIM3_CH2, TSC_G2_IO4, SPI1_MOSI, TIM1_CH1N, EVENTOUT; additional: ADC2_IN4 (fast channel), COMP2_INP, OPAMP2_VINP. |
| 14 | PB0 | bidirectional | 3.3 V TTa GPIO PB0; AF: TIM3_CH3, TSC_G3_IO2, TIM1_CH2N, EVENTOUT; additional: ADC1_IN11, COMP4_INP, OPAMP2_VINP; reset state: floating input. |
| 15 | PB1 | bidirectional | 3.3 V TTa GPIO PB1; AF: TIM3_CH4, TSC_G3_IO3, TIM1_CH3N, COMP4_OUT, EVENTOUT; additional: ADC1_IN12; reset state: floating input. |
| 16 | VSS | power_in | Digital ground reference; total current out of all VSS pins must not exceed 140 mA; must always be connected to external ground. |
| 17 | VDD | power_in | Main digital power supply, 2.0 to 3.6 V; decoupling capacitors required as close as possible to pin. |
| 18 | PA8 | bidirectional | 5 V-tolerant (FT) GPIO PA8; AF0: MCO (master clock output); AF6: TIM1_CH1; AF7: USART1_CK; AF15: EVENTOUT; reset state: floating input. |
| 19 | PA9 | bidirectional | 5 V-tolerant (FT) GPIO PA9; AF: TSC_G4_IO1, TIM1_CH2, USART1_TX, TIM15_BKIN, TIM2_CH3, EVENTOUT; reset state: floating input. |
| 20 | PA10 | bidirectional | 5 V-tolerant (FT) GPIO PA10; AF: TIM17_BKIN, TSC_G4_IO2, TIM1_CH3, USART1_RX, COMP6_OUT, TIM2_CH4, EVENTOUT; reset state: floating input. |
| 21 | PA11 | bidirectional | 5 V-tolerant (FT) GPIO PA11; AF: TIM1_CH1N, USART1_CTS, CAN_RX, TIM1_CH4, TIM1_BKIN2, EVENTOUT; reset state: floating input. |
| 22 | PA12 | bidirectional | 5 V-tolerant (FT) GPIO PA12; AF: TIM16_CH1, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT, CAN_TX, TIM1_ETR, EVENTOUT; reset state: floating input. |
| 23 | PA13 | bidirectional | 5 V-tolerant (FT) GPIO PA13; default function JTMS/SWDAT (SWD data line); AF: TIM16_CH1N, TSC_G4_IO3, IR_OUT, USART3_CTS, EVENTOUT. |
| 24 | PA14 | bidirectional | 5 V-tolerant FM+ capable (FTf) GPIO PA14; default function JTCK/SWCLK (SWD clock); AF: TSC_G4_IO4, I2C1_SDA, TIM1_BKIN, USART2_TX, EVENTOUT. |
| 25 | PA15 | bidirectional | 5 V-tolerant FM+ capable (FTf) GPIO PA15; default function JTDI; AF: TIM2_CH1/TIM2_ETR, TSC_SYNC, I2C1_SCL, SPI1_NSS, USART2_RX, TIM1_BKIN, EVENTOUT. |
| 26 | PB3 | bidirectional | 5 V-tolerant (FT) GPIO PB3; default function JTDO/TRACESWO; AF: TIM2_CH2, TSC_G5_IO1, SPI1_SCK, USART2_TX, TIM3_ETR, EVENTOUT. |
| 27 | PB4 | bidirectional | 5 V-tolerant (FT) GPIO PB4; default function NJTRST; AF: TIM16_CH1, TIM3_CH1, TSC_G5_IO2, SPI1_MISO, USART2_RX, TIM17_BKIN, EVENTOUT. |
| 28 | PB5 | bidirectional | 5 V-tolerant (FT) GPIO PB5; AF: TIM16_BKIN, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, USART2_CK, TIM17_CH1, EVENTOUT; reset state: floating input. |
| 29 | PB6 | bidirectional | 5 V-tolerant FM+ capable (FTf) GPIO PB6; AF: TIM16_CH1N, TSC_G5_IO3, I2C1_SCL, USART1_TX, EVENTOUT; supports I2C Fast-mode Plus (up to 1 Mbit/s) with 20 mA current sink. |
| 30 | PB7 | bidirectional | 5 V-tolerant FM+ capable (FTf) GPIO PB7; AF: TIM17_CH1N, TSC_G5_IO4, I2C1_SDA, USART1_RX, TIM3_CH4, EVENTOUT; reset state: floating input. |
| 31 | BOOT0 | input | Dedicated boot mode selection pin (B type); sampled at reset to select boot source (user Flash, system memory, or embedded SRAM); input voltage range 0 to 9 V; VIL max = VDD−0.3 V, VIH min = 0.2×VDD+0.95 V. |
| 32 | VSS | power_in | Digital ground reference; total current out of all VSS pins must not exceed 140 mA; must always be connected to external ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
CAD (KiCad official)
- Symbol:
STM32F303K8T6 - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32f303k8t6-etched.step/stm32f303k8t6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f303k8t6.step/stm32f303k8t6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (115 pp, sha256
dc1490452e89dccc, retrieved 2026-09-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).