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STM32F302RET6TR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f302ret6trfactory-2.0.0extractor-text
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STM32F302RET6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F302RET6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply pin (VBAT) for the RTC and backup registers.
2 PC13 bidirectional Standard 3.3 V I/O (WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT, TIM1_CH1N, EVENTOUT) supplied through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz at 30 pF and it must not source current such as LED drive.
3 PC14 bidirectional Standard 3.3 V I/O shared with OSC32_IN and supplied through the power switch (3 mA limit), so output speed must not exceed 2 MHz at 30 pF and it must not be used as a current source.
4 PC15 bidirectional Standard 3.3 V I/O shared with OSC32_OUT and supplied through the power switch (3 mA limit), so output speed must not exceed 2 MHz at 30 pF and it must not be used as a current source.
5 PF0-OSC_IN input 5 V tolerant FTf pin (I2C FM+ option) that serves as the OSC_IN oscillator input, with alternate functions I2C2_SDA, SPI2_NSS/I2S2_WS and TIM1_CH3N.
6 PF1-OSC_OUT output 5 V tolerant FTf pin (I2C FM+ option) that serves as the OSC_OUT oscillator output, with alternate functions I2C2_SCL and SPI2_SCK/I2S2_CK.
7 NRST bidirectional Bi-directional device reset pin with embedded weak pull-up; it is the reset input and internal reset output, active low.
8 PC0 bidirectional 3.3 V tolerant TTa I/O with ADC12_IN6 analog input, plus alternate functions EVENTOUT and TIM1_CH1.
9 PC1 bidirectional 3.3 V tolerant TTa I/O with ADC12_IN7 analog input, plus alternate functions EVENTOUT and TIM1_CH2.
10 PC2 bidirectional 3.3 V tolerant TTa I/O with ADC12_IN8 analog input, plus alternate functions EVENTOUT and TIM1_CH3.
11 PC3 bidirectional 3.3 V tolerant TTa I/O with ADC12_IN9 analog input, plus alternate functions EVENTOUT, TIM1_CH4 and TIM1_BKIN2.
12 VSSA power_in Analog ground pin (VSSA) for the analog peripherals.
13 VDDA power_in Analog supply pin (VDDA) for the analog peripherals, specified from 2.0 V to 3.6 V; on this 64-pin package VREF+ is internally connected to VDDA.
14 PA0 bidirectional 3.3 V tolerant TTa I/O with alternate functions TIM2_CH1/TIM2_ETR, TSC_G1_IO1, USART2_CTS, COMP1_OUT and EVENTOUT, and additional functions ADC1_IN1, COMP1_INM, RTC_TAMP2 and WKUP1.
15 PA1 bidirectional 3.3 V tolerant TTa I/O with alternate functions RTC_REFIN, TIM2_CH2, TSC_G1_IO2, USART2_RTS, TIM15_CH1N and EVENTOUT, and additional functions ADC1_IN2, COMP1_INP and OPAMP1_VINP.
16 PA2 bidirectional 3.3 V tolerant TTa I/O with reduced touch sensing sensitivity (recommended as sampling capacitor I/O), alternate functions TIM2_CH3, TSC_G1_IO3, USART2_TX, COMP2_OUT, TIM15_CH1 and EVENTOUT, and additional functions ADC1_IN3, COMP2_INM and OPAMP1_VOUT.
17 PA3 bidirectional 3.3 V tolerant TTa I/O with alternate functions TIM2_CH4, TSC_G1_IO4, USART2_RX, TIM15_CH2 and EVENTOUT, and additional functions ADC1_IN4, OPAMP1_VINM and OPAMP1_VINP.
18 VSS power_in Digital ground pin (VSS) of the device.
19 VDD power_in Digital supply pin (VDD), specified from 2.0 V to 3.6 V.
20 PA4 bidirectional 3.3 V tolerant TTa I/O with reduced touch sensing sensitivity, alternate functions TIM3_CH2, TSC_G2_IO1, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK and EVENTOUT, and additional functions ADC2_IN1, DAC1_OUT1 and several COMP inverting inputs.
21 PA5 bidirectional 3.3 V tolerant TTa I/O with reduced touch sensing sensitivity, alternate functions TIM2_CH1/TIM2_ETR, TSC_G2_IO2, SPI1_SCK and EVENTOUT, and additional functions ADC2_IN2, COMP inverting inputs, OPAMP1_VINP and OPAMP2_VINM.
22 PA6 bidirectional 3.3 V tolerant TTa I/O with reduced touch sensing sensitivity, alternate functions TIM16_CH1, TIM3_CH1, TSC_G2_IO3, SPI1_MISO, TIM1_BKIN, COMP1_OUT and EVENTOUT, and additional functions ADC2_IN3 and OPAMP2_VOUT.
23 PA7 bidirectional 3.3 V tolerant TTa I/O with alternate functions TIM17_CH1, TIM3_CH2, TSC_G2_IO4, SPI1_MOSI, TIM1_CH1N and EVENTOUT, and additional functions ADC2_IN4, COMP2_INP, OPAMP1_VINP and OPAMP2_VINP.
24 PC4 bidirectional 3.3 V tolerant TTa I/O with alternate functions EVENTOUT, TIM1_ETR and USART1_TX, and additional function ADC2_IN5.
25 PC5 bidirectional 3.3 V tolerant TTa I/O with alternate functions EVENTOUT, TIM15_BKIN, TSC_G3_IO1 and USART1_RX, and additional functions ADC2_IN11, OPAMP1_VINM and OPAMP2_VINM.
26 PB0 bidirectional 3.3 V tolerant TTa I/O with alternate functions TIM3_CH3, TSC_G3_IO2, TIM1_CH2N and EVENTOUT, and additional functions COMP4_INP and OPAMP2_VINP.
27 PB1 bidirectional 3.3 V tolerant TTa I/O with reduced touch sensing sensitivity, alternate functions TIM3_CH4, TSC_G3_IO3, TIM1_CH3N, COMP4_OUT and EVENTOUT.
28 PB2 bidirectional 3.3 V tolerant TTa I/O with alternate functions TSC_G3_IO4 and EVENTOUT, and additional functions ADC2_IN12 and COMP4_INM.
29 PB10 bidirectional 3.3 V tolerant TTa I/O with alternate functions TIM2_CH3, TSC_SYNC, USART3_TX and EVENTOUT.
30 PB11 bidirectional 3.3 V tolerant TTa I/O with alternate functions TIM2_CH4, TSC_G6_IO1, USART3_RX and EVENTOUT, and additional functions ADC12_IN14 and COMP6_INP.
31 VSS power_in Digital ground pin (VSS) of the device.
32 VDD power_in Digital supply pin (VDD), specified from 2.0 V to 3.6 V.
33 PB12 bidirectional 3.3 V tolerant TTa I/O with reduced touch sensing sensitivity, alternate functions TSC_G6_IO2, I2C2_SMBAL, SPI2_NSS/I2S2_WS, TIM1_BKIN, USART3_CK and EVENTOUT.
34 PB13 bidirectional 3.3 V tolerant TTa I/O with alternate functions TSC_G6_IO3, SPI2_SCK/I2S2_CK, TIM1_CH1N, USART3_CTS and EVENTOUT.
35 PB14 bidirectional 3.3 V tolerant TTa I/O with alternate functions TIM15_CH1, TSC_G6_IO4, SPI2_MISO/I2S2ext_SD, TIM1_CH2N, USART3_RTS and EVENTOUT, and additional function OPAMP2_VINP.
36 PB15 bidirectional 3.3 V tolerant TTa I/O with alternate functions RTC_REFIN, TIM15_CH2, TIM15_CH1N, TIM1_CH3N, SPI2_MOSI/I2S2_SD and EVENTOUT, and additional function COMP6_INM.
37 PC6 bidirectional 5 V tolerant FT I/O with alternate functions EVENTOUT, TIM3_CH1, I2S2_MCK and COMP6_OUT.
38 PC7 bidirectional 5 V tolerant FT I/O with alternate functions EVENTOUT, TIM3_CH2 and I2S3_MCK.
39 PC8 bidirectional 5 V tolerant FT I/O with alternate functions EVENTOUT and TIM3_CH3.
40 PC9 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions EVENTOUT, TIM3_CH4, I2C3_SDA and I2SCKIN.
41 PA8 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions MCO, I2C3_SCL, I2C2_SMBAL, I2S2_MCK, TIM1_CH1, USART1_CK, TIM4_ETR and EVENTOUT.
42 PA9 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions I2C3_SMBAL, TSC_G4_IO1, I2C2_SCL, I2S3_MCK, TIM1_CH2, USART1_TX, TIM15_BKIN, TIM2_CH3 and EVENTOUT.
43 PA10 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions TIM17_BKIN, TSC_G4_IO2, I2C2_SDA, SPI2_MISO/I2S2ext_SD, TIM1_CH3, USART1_RX, COMP6_OUT, TIM2_CH4 and EVENTOUT.
44 PA11 bidirectional 5 V tolerant FT I/O with alternate functions SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, COMP1_OUT, CAN_RX, TIM4_CH1, TIM1_CH4, TIM1_BKIN2 and EVENTOUT, and additional function USB_DM.
45 PA12 bidirectional 5 V tolerant FT I/O with alternate functions TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS, COMP2_OUT, CAN_TX, TIM4_CH2, TIM1_ETR and EVENTOUT, and additional function USB_DP.
46 PA13 bidirectional 5 V tolerant FT I/O with alternate functions SWDIO-JTMS, TIM16_CH1N, TSC_G4_IO3, IR-OUT, USART3_CTS, TIM4_CH3 and EVENTOUT.
47 VSS power_in Digital ground pin (VSS) of the device.
48 VDD power_in Digital supply pin (VDD), specified from 2.0 V to 3.6 V.
49 PA14 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions SWCLK-JTCK, TSC_G4_IO4, I2C1_SDA, TIM1_BKIN, USART2_TX and EVENTOUT.
50 PA15 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions JTDI, TIM2_CH1/TIM2_ETR, TSC_SYNC, I2C1_SCL, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_RX, TIM1_BKIN and EVENTOUT.
51 PC10 bidirectional 5 V tolerant FT I/O with alternate functions EVENTOUT, UART4_TX, SPI3_SCK/I2S3_CK and USART3_TX.
52 PC11 bidirectional 5 V tolerant FT I/O with alternate functions EVENTOUT, UART4_RX, SPI3_MISO/I2S3ext_SD and USART3_RX.
53 PC12 bidirectional 5 V tolerant FT I/O with alternate functions EVENTOUT, UART5_TX, SPI3_MOSI/I2S3_SD and USART3_CK.
54 PD2 bidirectional 5 V tolerant FT I/O with alternate functions EVENTOUT, TIM3_ETR and UART5_RX.
55 PB3 bidirectional 5 V tolerant FT I/O with alternate functions JTDO-TRACESWO, TIM2_CH2, TIM4_ETR, TSC_G5_IO1, SPI1_SCK, SPI3_SCK/I2S3_CK, USART2_TX, TIM3_ETR and EVENTOUT.
56 PB4 bidirectional 5 V tolerant FT I/O with alternate functions JTRST, TIM16_CH1, TIM3_CH1, TSC_G5_IO2, SPI1_MISO, SPI3_MISO/I2S3ext_SD, USART2_RX, TIM17_BKIN and EVENTOUT.
57 PB5 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions TIM16_BKIN, TIM3_CH2, I2C1_SMBAL, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA, TIM17_CH1 and EVENTOUT.
58 PB6 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions TIM16_CH1N, TIM4_CH1, TSC_G5_IO3, I2C1_SCL, USART1_TX and EVENTOUT.
59 PB7 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions TIM17_CH1N, TIM4_CH2, TSC_G5_IO4, I2C1_SDA, USART1_RX, TIM3_CH4, FMC_NADV and EVENTOUT.
60 BOOT0 input Dedicated BOOT0 pin, typed as a plain input with no I/O structure given in the pin table.
61 PB8 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions TIM16_CH1, TIM4_CH3, TSC_SYNC, I2C1_SCL, USART3_RX, COMP1_OUT, CAN_RX, TIM1_BKIN and EVENTOUT.
62 PB9 bidirectional 5 V tolerant FTf I/O (I2C FM+ option) with alternate functions TIM17_CH1, TIM4_CH4, I2C1_SDA, IR-OUT, USART3_TX, COMP2_OUT, CAN_TX and EVENTOUT.
63 VSS power_in Digital ground pin (VSS) of the device.
64 VDD power_in Digital supply pin (VDD), specified from 2.0 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32F302RET6TR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f302ret6tr-etched.step / stm32f302ret6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f302ret6tr.step / stm32f302ret6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (168 pp, sha256 9adaf87c56f80b2f, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF