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STM32F302RET6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f302ret6factory-2.0.0extractor-text

Verified STM32F302RET6

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: STM32F302RET6 · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 168-page datasheet
  • ✓distributor: lcsc C1337374, digikey 497-17418-ND, mouser 511-STM32F302RET6
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-do5nle7_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ stm32f302ret6.kicad_sym✓ stm32f302ret6.kicad_mod✓ stm32f302ret6.step
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Ray Publish 0.1.0 061b159 5h ago

STM32F302RET6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F302RET6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup domain supply for the RTC and backup registers.
2 PC13 bidirectional Standard 3.3 V I/O (TC) on the backup power switch, which sinks only 3 mA, so output speed is limited to 2 MHz at 30 pF and it must not be used as a current source; alternate functions EVENTOUT, TIM1_CH1N; additional functions WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT.
3 PC14 bidirectional Standard 3.3 V I/O (TC) on the backup power switch, with the same 3 mA limit and 2 MHz at 30 pF output limit, also used as OSC32_IN.
4 PC15 bidirectional Standard 3.3 V I/O (TC) on the backup power switch, with the same 3 mA limit and 2 MHz at 30 pF output limit, also used as OSC32_OUT.
5 PF0-OSC_IN input 5 V tolerant I/O (FTf, I2C FM+ option) used as OSC_IN for the external crystal oscillator; alternate functions EVENTOUT, I2C2_SDA, SPI2_NSS/I2S2_WS, TIM1_CH3N.
6 PF1-OSC_OUT output 5 V tolerant I/O (FTf, I2C FM+ option) used as OSC_OUT for the external crystal oscillator; alternate functions EVENTOUT, I2C2_SCL, SPI2_SCK/I2S2_CK.
7 NRST bidirectional Bi-directional reset pin with embedded weak pull-up resistor, acting as device reset input and internal reset output (active low).
8 PC0 bidirectional 3.3 V tolerant I/O (TTa); alternate functions EVENTOUT, TIM1_CH1; additional function ADC12_IN6.
9 PC1 bidirectional 3.3 V tolerant I/O (TTa); alternate functions EVENTOUT, TIM1_CH2; additional function ADC12_IN7.
10 PC2 bidirectional 3.3 V tolerant I/O (TTa); alternate functions EVENTOUT, TIM1_CH3; additional function ADC12_IN8.
11 PC3 bidirectional 3.3 V tolerant I/O (TTa); alternate functions EVENTOUT, TIM1_CH4, TIM1_BKIN2; additional function ADC12_IN9.
12 VSSA power_in Analog ground pin (VSSA).
13 VDDA power_in Analog supply voltage, 2.0 V to 3.6 V; on the 64-pin package VREF+ is internally connected to VDDA.
14 PA0 bidirectional 3.3 V tolerant I/O (TTa); alternate functions TIM2_CH1/TIM2_ETR, TSC_G1_IO1, USART2_CTS, COMP1_OUT, EVENTOUT; additional functions ADC1_IN1, COMP1_INM, RTC_TAMP2, WKUP1.
15 PA1 bidirectional 3.3 V tolerant I/O (TTa); alternate functions RTC_REFIN, TIM2_CH2, TSC_G1_IO2, USART2_RTS, TIM15_CH1N, EVENTOUT; additional functions ADC1_IN2, COMP1_INP, OPAMP1_VINP.
16 PA2 bidirectional 3.3 V tolerant I/O (TTa) with reduced touch sensing sensitivity, recommended as sampling capacitor I/O; alternate functions TIM2_CH3, TSC_G1_IO3, USART2_TX, COMP2_OUT, TIM15_CH1, EVENTOUT; additional functions ADC1_IN3, COMP2_INM, OPAMP1_VOUT.
17 PA3 bidirectional 3.3 V tolerant I/O (TTa); alternate functions TIM2_CH4, TSC_G1_IO4, USART2_RX, TIM15_CH2, EVENTOUT; additional functions ADC1_IN4, OPAMP1_VINM/OPAMP1_VINP.
18 VSS power_in Ground pin (VSS).
19 VDD power_in Power supply pin, 2.0 V to 3.6 V.
20 PA4 bidirectional 3.3 V tolerant I/O (TTa) with reduced touch sensing sensitivity; alternate functions TIM3_CH2, TSC_G2_IO1, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, EVENTOUT; additional functions ADC2_IN1, DAC1_OUT1, COMP1_INM, COMP2_INM, COMP4_INM, COMP6_INM.
21 PA5 bidirectional 3.3 V tolerant I/O (TTa) with reduced touch sensing sensitivity; alternate functions TIM2_CH1/TIM2_ETR, TSC_G2_IO2, SPI1_SCK, EVENTOUT; additional functions ADC2_IN2, COMP1_INM, COMP2_INM, COMP4_INM, COMP6_INM, OPAMP1_VINP, OPAMP2_VINM.
22 PA6 bidirectional 3.3 V tolerant I/O (TTa) with reduced touch sensing sensitivity; alternate functions TIM16_CH1, TIM3_CH1, TSC_G2_IO3, SPI1_MISO, TIM1_BKIN, COMP1_OUT, EVENTOUT; additional functions ADC2_IN3, OPAMP2_VOUT.
23 PA7 bidirectional 3.3 V tolerant I/O (TTa); alternate functions TIM17_CH1, TIM3_CH2, TSC_G2_IO4, SPI1_MOSI, TIM1_CH1N, EVENTOUT; additional functions ADC2_IN4, COMP2_INP, OPAMP1_VINP, OPAMP2_VINP.
24 PC4 bidirectional 3.3 V tolerant I/O (TTa); alternate functions EVENTOUT, TIM1_ETR, USART1_TX; additional function ADC2_IN5.
25 PC5 bidirectional 3.3 V tolerant I/O (TTa); alternate functions EVENTOUT, TIM15_BKIN, TSC_G3_IO1, USART1_RX; additional functions ADC2_IN11, OPAMP1_VINM, OPAMP2_VINM.
26 PB0 bidirectional 3.3 V tolerant I/O (TTa); alternate functions TIM3_CH3, TSC_G3_IO2, TIM1_CH2N, EVENTOUT; additional functions COMP4_INP, OPAMP2_VINP.
27 PB1 bidirectional 3.3 V tolerant I/O (TTa) with reduced touch sensing sensitivity; alternate functions TIM3_CH4, TSC_G3_IO3, TIM1_CH3N, COMP4_OUT, EVENTOUT.
28 PB2 bidirectional 3.3 V tolerant I/O (TTa); alternate functions TSC_G3_IO4, EVENTOUT; additional functions ADC2_IN12, COMP4_INM.
29 PB10 bidirectional 3.3 V tolerant I/O (TTa); alternate functions TIM2_CH3, TSC_SYNC, USART3_TX, EVENTOUT.
30 PB11 bidirectional 3.3 V tolerant I/O (TTa); alternate functions TIM2_CH4, TSC_G6_IO1, USART3_RX, EVENTOUT; additional functions ADC12_IN14, COMP6_INP.
31 VSS power_in Ground pin (VSS).
32 VDD power_in Power supply pin, 2.0 V to 3.6 V.
33 PB12 bidirectional 3.3 V tolerant I/O (TTa) with reduced touch sensing sensitivity; alternate functions TSC_G6_IO2, I2C2_SMBAL, SPI2_NSS/I2S2_WS, TIM1_BKIN, USART3_CK, EVENTOUT.
34 PB13 bidirectional 3.3 V tolerant I/O (TTa); alternate functions TSC_G6_IO3, SPI2_SCK/I2S2_CK, TIM1_CH1N, USART3_CTS, EVENTOUT.
35 PB14 bidirectional 3.3 V tolerant I/O (TTa); alternate functions TIM15_CH1, TSC_G6_IO4, SPI2_MISO/I2S2ext_SD, TIM1_CH2N, USART3_RTS, EVENTOUT; additional function OPAMP2_VINP.
36 PB15 bidirectional 3.3 V tolerant I/O (TTa); alternate functions RTC_REFIN, TIM15_CH2, TIM15_CH1N, TIM1_CH3N, SPI2_MOSI/I2S2_SD, EVENTOUT; additional function COMP6_INM.
37 PC6 bidirectional 5 V tolerant I/O (FT); alternate functions EVENTOUT, TIM3_CH1, I2S2_MCK, COMP6_OUT.
38 PC7 bidirectional 5 V tolerant I/O (FT); alternate functions EVENTOUT, TIM3_CH2, I2S3_MCK.
39 PC8 bidirectional 5 V tolerant I/O (FT); alternate functions EVENTOUT, TIM3_CH3.
40 PC9 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions EVENTOUT, TIM3_CH4, I2C3_SDA, I2SCKIN.
41 PA8 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions MCO, I2C3_SCL, I2C2_SMBAL, I2S2_MCK, TIM1_CH1, USART1_CK, TIM4_ETR, EVENTOUT.
42 PA9 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions I2C3_SMBAL, TSC_G4_IO1, I2C2_SCL, I2S3_MCK, TIM1_CH2, USART1_TX, TIM15_BKIN, TIM2_CH3, EVENTOUT.
43 PA10 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions TIM17_BKIN, TSC_G4_IO2, I2C2_SDA, SPI2_MISO/I2S2ext_SD, TIM1_CH3, USART1_RX, COMP6_OUT, TIM2_CH4, EVENTOUT.
44 PA11 bidirectional 5 V tolerant I/O (FT); alternate functions SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, COMP1_OUT, CAN_RX, TIM4_CH1, TIM1_CH4, TIM1_BKIN2, EVENTOUT; additional function USB_DM.
45 PA12 bidirectional 5 V tolerant I/O (FT); alternate functions TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS, COMP2_OUT, CAN_TX, TIM4_CH2, TIM1_ETR, EVENTOUT; additional function USB_DP.
46 PA13 bidirectional 5 V tolerant I/O (FT); alternate functions SWDIO-JTMS, TIM16_CH1N, TSC_G4_IO3, IR-OUT, USART3_CTS, TIM4_CH3, EVENTOUT.
47 VSS power_in Ground pin (VSS).
48 VDD power_in Power supply pin, 2.0 V to 3.6 V.
49 PA14 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions SWCLK-JTCK, TSC_G4_IO4, I2C1_SDA, TIM1_BKIN, USART2_TX, EVENTOUT.
50 PA15 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions JTDI, TIM2_CH1/TIM2_ETR, TSC_SYNC, I2C1_SCL, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_RX, TIM1_BKIN, EVENTOUT.
51 PC10 bidirectional 5 V tolerant I/O (FT); alternate functions EVENTOUT, UART4_TX, SPI3_SCK/I2S3_CK, USART3_TX.
52 PC11 bidirectional 5 V tolerant I/O (FT); alternate functions EVENTOUT, UART4_RX, SPI3_MISO/I2S3ext_SD, USART3_RX.
53 PC12 bidirectional 5 V tolerant I/O (FT); alternate functions EVENTOUT, UART5_TX, SPI3_MOSI/I2S3_SD, USART3_CK.
54 PD2 bidirectional 5 V tolerant I/O (FT); alternate functions EVENTOUT, TIM3_ETR, UART5_RX.
55 PB3 bidirectional 5 V tolerant I/O (FT); alternate functions JTDO-TRACESWO, TIM2_CH2, TIM4_ETR, TSC_G5_IO1, SPI1_SCK, SPI3_SCK/I2S3_CK, USART2_TX, TIM3_ETR, EVENTOUT.
56 PB4 bidirectional 5 V tolerant I/O (FT); alternate functions JTRST, TIM16_CH1, TIM3_CH1, TSC_G5_IO2, SPI1_MISO, SPI3_MISO/I2S3ext_SD, USART2_RX, TIM17_BKIN, EVENTOUT.
57 PB5 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions TIM16_BKIN, TIM3_CH2, I2C1_SMBAl, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA, TIM17_CH1, EVENTOUT.
58 PB6 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions TIM16_CH1N, TIM4_CH1, TSC_G5_IO3, I2C1_SCL, USART1_TX, EVENTOUT.
59 PB7 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions TIM17_CH1N, TIM4_CH2, TSC_G5_IO4, I2C1_SDA, USART1_RX, TIM3_CH4, FMC_NADV, EVENTOUT.
60 BOOT0 input Dedicated BOOT0 pin, used for boot mode selection.
61 PB8 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions TIM16_CH1, TIM4_CH3, TSC_SYNC, I2C1_SCL, USART3_RX, COMP1_OUT, CAN_RX, TIM1_BKIN, EVENTOUT.
62 PB9 bidirectional 5 V tolerant I/O (FTf, I2C FM+ option); alternate functions TIM17_CH1, TIM4_CH4, I2C1_SDA, IR-OUT, USART3_TX, COMP2_OUT, CAN_TX, EVENTOUT.
63 VSS power_in Ground pin (VSS).
64 VDD power_in Power supply pin, 2.0 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (VDD, VDDA, VBAT) VDD-VSS VDD-VSS -0.3 4 V 66
Input voltage on TTa pins VIN -0.3 4 V Input voltage on TTa pins 66
Input voltage on any other pin VIN -0.3 4 V Input voltage on any other pin 66
Input voltage on Boot0 pin VIN 0 9 V Input voltage on Boot0 pin 66
Allowed voltage difference for VDD > VDDA VDD-VDDA 0.4 V VDD > VDDA 66
Variations between different VDD power pins /ΔVDDx/ 50 mV 66
Variations between all the different ground pins /VSSX-VSS/ 50 mV 66
Total current into sum of all VDD_x power lines (source) ΣIVDD 160 mA 67
Total current out of sum of all VSS_x ground lines (sink) ΣIVSS -160 mA 67
Maximum current into each VDD_x power line (source) IVDD 100 mA 67
Maximum current out of each VSS_x ground line (sink) IVSS 100 mA 67
Output current sunk by any I/O and control pin IIO(PIN) 25 mA 67
Output current source by any I/O and control pin IIO(PIN) -25 mA 67
Total output current sunk by sum of all IOs and control pins ΣIIO(PIN) 80 mA 67
Total output current sourced by sum of all IOs and control pins ΣIIO(PIN) -80 mA 67
Injected current on FT, FTf, and B pins IINJ(PIN) -5 0 mA 67
Injected current on TC and RST pin IINJ(PIN) -5 5 mA 67
Injected current on TTa pins IINJ(PIN) -5 5 mA 67
Total injected current (sum of all I/O and control pins) ΣIINJ(PIN) -25 25 mA 67
Storage temperature range TSTG -65 150 °C 67
Maximum junction temperature TJ 150 °C 67
Internal AHB clock frequency fHCLK 0 72 MHz 68
Internal APB1 clock frequency fPCLK1 0 36 MHz 68
Internal APB2 clock frequency fPCLK2 0 72 MHz 68
Standard operating voltage VDD 2 3.6 V 68
Analog operating voltage VDDA 2 3.6 V OPAMP and DAC not used; must be equal to or higher than VDD 68
Analog operating voltage VDDA 2.4 3.6 V OPAMP and DAC used 68
Backup operating voltage VBAT 1.65 3.6 V 68
FT and FTf I/O input voltage VIN -0.3 5.5 V FT and FTf I/O 68
BOOT0 input voltage VIN 0 5.5 V BOOT0 68
Power dissipation LQFP64 PD 435 mW TA = 85 °C for suffix 6 68
Ambient temperature for 6 suffix version TA -40 85 °C Maximum power dissipation 68
Junction temperature range, 6 suffix version TJ -40 105 °C 6 suffix version 68
Power on/power down reset threshold, falling edge VPOR/PDR 1.8 1.88 1.96 V Falling edge 69
Power on/power down reset threshold, rising edge VPOR/PDR 1.84 1.92 2 V Rising edge 69
PDR hysteresis VPDRhyst 40 mV 69
PVD threshold 0, rising edge VPVD0 2.1 2.18 2.26 V Rising edge 69
PVD threshold 0, falling edge VPVD0 2 2.08 2.16 V Falling edge 69
PVD threshold 7, rising edge VPVD7 2.76 2.88 3 V Rising edge 69
PVD threshold 7, falling edge VPVD7 2.66 2.78 2.9 V Falling edge 69
PVD hysteresis VPVDhyst 100 mV Guaranteed by design, not tested in production 69
Internal reference voltage VREFINT 1.16 1.2 1.25 V -40 °C < TA < +105 °C 70
Internal reference voltage VREFINT 1.16 1.2 1.24 V -40 °C < TA < +85 °C 70
Internal reference voltage spread over the temperature range VRERINT 10 mV VDD = 3 V ±10 mV 70
Temperature coefficient TCoeff 100 ppm/°C 70
ADC sampling time when reading the internal reference voltage TS_vrefint 2.2 µs 70
High-speed external user clock source frequency fHSE_ext 1 8 32 MHz User external clock source frequency 83
OSC_IN high or low time tw(HSEH) tw(HSEL) 15 ns 83
OSC_IN rise or fall time tr(HSE) tf(HSE) 20 ns 83
User External clock source frequency (LSE) fLSE_ext 32.768 1000 kHz User External clock source frequency 84
OSC32_IN high or low time tw(LSEH) tw(LSEL) 450 ns 84
Oscillator frequency (HSE) fOSC_IN 4 8 32 MHz 85
HSE startup time tSU(HSE) 2 ms VDD is stabilized 85
HSI frequency fHSI 8 MHz 87
Accuracy of the HSI oscillator ACCHSI -2.8 3.8 % TA = -40 to 105°C; VDDA = 3.3 V 87
Frequency (LSI) fLSI 30 40 50 kHz VDDA = 3.3 V, TA = -40 to 105 °C 88
PLL input clock fPLL_IN 1 24 MHz 88
PLL multiplier output clock fPLL_OUT 16 72 MHz 88
PLL lock time tLOCK 200 µs 88
16-bit programming time tprog 40 53.5 60 µs TA = -40 to +105 °C 89

CAD (KiCad official)

  • Symbol: STM32F302RET6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f302ret6-etched.step / stm32f302ret6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f302ret6.step / stm32f302ret6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (168 pp, sha256 9adaf87c56f80b2f, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF