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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM32F302CBT6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32F302CBT6TR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Backup power supply (1.65 V to 3.6 V) for RTC, 32 kHz oscillator, and 64-byte backup registers when VDD is absent.
2	PC13	bidirectional	GPIO (TC type, power-switch supplied ≤3 mA, ≤2 MHz, ≤30 pF); AF TIM1_CH1N; additional WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT.
3	PC14/OSC32_IN	bidirectional	GPIO (TC type, power-switch supplied ≤3 mA, ≤2 MHz); default function OSC32_IN for the 32.768 kHz crystal oscillator.
4	PC15/OSC32_OUT	bidirectional	GPIO (TC type, power-switch supplied ≤3 mA, ≤2 MHz); default function OSC32_OUT for the 32.768 kHz crystal oscillator.
5	PF0/OSC_IN	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); default function OSC_IN for 4-32 MHz HSE crystal oscillator; AF TIM1_CH3N, I2C2_SDA.
6	PF1/OSC_OUT	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); default function OSC_OUT for the HSE oscillator; AF I2C2_SCL.
7	NRST	input	Bidirectional reset pin with embedded 25-55 kΩ weak pull-up; active-low; pulses < 100 ns are filtered, ≥ 500 ns guaranteed to reset device.
8	VSSA/VREF-	power_in	Analog ground and negative ADC reference voltage for ADC, DAC, comparators, and OPAMPs; must be connected to ground.
9	VDDA/VREF+	power_in	Analog power supply (2.0 V to 3.6 V) and positive ADC reference; on LQFP48 VREF+ is internally connected to VDDA (no separate VREF+ pin).
10	PA0	bidirectional	GPIO (TTa, fast ADC channel); ADC1_IN1; AF USART2_CTS, TIM2_CH1_ETR, TSC_G1_IO1, COMP1_OUT, EVENTOUT; additional WKUP1, RTC_TAMP2, COMP1_INM.
11	PA1	bidirectional	GPIO (TTa, fast ADC channel); ADC1_IN2; AF USART2_RTS_DE, TIM2_CH2, TIM15_CH1N, RTC_REFIN, TSC_G1_IO2, EVENTOUT; additional COMP1_INP, OPAMP1_VINP.
12	PA2	bidirectional	GPIO (TTa, fast ADC channel, reduced TSC sensitivity); ADC1_IN3; AF USART2_TX, TIM2_CH3, TIM15_CH1, TSC_G1_IO3, COMP2_OUT, EVENTOUT; additional OPAMP1_VOUT, COMP2_INM.
13	PA3	bidirectional	GPIO (TTa, fast ADC channel); ADC1_IN4; AF USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4, EVENTOUT; additional OPAMP1_VINP, COMP2_INP, OPAMP1_VINM.
14	PA4	bidirectional	GPIO (TTa, fast ADC channel, reduced TSC sensitivity-recommended as sampling capacitor I/O); ADC2_IN1, DAC1_OUT1; AF SPI1_NSS, SPI3_NSS, I2S3_WS, USART2_CK, TIM3_CH2, TSC_G2_IO1, EVENTOUT.
15	PA5	bidirectional	GPIO (TTa, fast ADC channel, reduced TSC sensitivity-recommended as sampling capacitor I/O); ADC2_IN2; AF SPI1_SCK, TIM2_CH1_ETR, TSC_G2_IO2, EVENTOUT; additional OPAMP1_VINP, OPAMP2_VINM.
16	PA6	bidirectional	GPIO (TTa, fast ADC channel, reduced TSC sensitivity-recommended as sampling capacitor I/O); ADC2_IN3; AF SPI1_MISO, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT; additional OPAMP2_VOUT.
17	PA7	bidirectional	GPIO (TTa, fast ADC channel); ADC2_IN4; AF SPI1_MOSI, TIM3_CH2, TIM17_CH1, TIM1_CH1N, TSC_G2_IO4, COMP2_OUT, EVENTOUT; additional COMP2_INP, OPAMP2_VINP, OPAMP1_VINP.
18	PB0	bidirectional	GPIO (TTa type); AF TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT; additional COMP4_INP, OPAMP2_VINP.
19	PB1	bidirectional	GPIO (TTa type, reduced TSC sensitivity); AF TIM3_CH4, TIM1_CH3N, COMP4_OUT, TSC_G3_IO3, EVENTOUT.
20	PB2	bidirectional	GPIO (TTa type); ADC2_IN12; AF TSC_G3_IO4, EVENTOUT; additional COMP4_INM.
21	PB10	bidirectional	GPIO (TTa type); AF USART3_TX, TIM2_CH3, TSC_SYNC, EVENTOUT.
22	PB11	bidirectional	GPIO (TTa type); AF USART3_RX, TIM2_CH4, TSC_G6_IO1, EVENTOUT; additional COMP6_INP.
23	VSS	power_in	Digital ground; 0 V reference for core logic and I/Os.
24	VDD	power_in	Digital power supply, 2.0 V to 3.6 V, for I/Os and internal voltage regulator.
25	PB12	bidirectional	GPIO (TTa type, reduced TSC sensitivity); AF SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, TSC_G6_IO2, EVENTOUT.
26	PB13	bidirectional	GPIO (TTa type); AF SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, TSC_G6_IO3, EVENTOUT.
27	PB14	bidirectional	GPIO (TTa type); AF SPI2_MISO/I2S2ext_SD, USART3_RTS_DE, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4, EVENTOUT; additional OPAMP2_VINP.
28	PB15	bidirectional	GPIO (TTa type); AF SPI2_MOSI/I2S2_SD, TIM1_CH3N, RTC_REFIN, TIM15_CH1N, TIM15_CH2, EVENTOUT; additional COMP6_INM.
29	PA8	bidirectional	GPIO (FT, 5 V-tolerant); AF I2C2_SMBA, I2S2_MCK, USART1_CK, TIM1_CH1, TIM4_ETR, MCO, EVENTOUT.
30	PA9	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); AF I2C2_SCL, I2S3_MCK, USART1_TX, TIM1_CH2, TIM2_CH3, TIM15_BKIN, TSC_G4_IO1, EVENTOUT.
31	PA10	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); AF I2C2_SDA, USART1_RX, TIM1_CH3, TIM2_CH4, TIM17_BKIN, TSC_G4_IO2, COMP6_OUT, EVENTOUT.
32	PA11	bidirectional	GPIO (FT, 5 V-tolerant); AF USART1_CTS, USB_DM, CAN_RX, TIM1_CH1N, TIM1_CH4, TIM1_BKIN2, TIM4_CH1, COMP1_OUT, EVENTOUT.
33	PA12	bidirectional	GPIO (FT, 5 V-tolerant); AF USART1_RTS_DE, USB_DP, CAN_TX, TIM1_CH2N, TIM1_ETR, TIM4_CH2, TIM16_CH1, COMP2_OUT, EVENTOUT.
34	PA13	bidirectional	GPIO (FT, 5 V-tolerant); default SWDIO/JTMS after reset (AF0); AF USART3_CTS, TIM4_CH3, TIM16_CH1N, TSC_G4_IO3, IR_OUT, EVENTOUT.
35	VSS	power_in	Digital ground; 0 V reference for core logic and I/Os.
36	VDD	power_in	Digital power supply, 2.0 V to 3.6 V, for I/Os and internal voltage regulator.
37	PA14	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); default SWCLK/JTCK after reset (AF0); AF I2C1_SDA, USART2_TX, TIM1_BKIN, TSC_G4_IO4, EVENTOUT.
38	PA15	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); default JTDI after reset (AF0); AF I2C1_SCL, SPI1_NSS, SPI3_NSS, I2S3_WS, USART2_RX, TIM1_BKIN, TIM2_CH1_ETR, EVENTOUT.
39	PB3	bidirectional	GPIO (FT, 5 V-tolerant); default JTDO/TRACESWO after reset (AF0); AF SPI3_SCK/I2S3_CK, SPI1_SCK, USART2_TX, TIM2_CH2, TIM3_ETR, TIM4_ETR, TSC_G5_IO1, EVENTOUT.
40	PB4	bidirectional	GPIO (FT, 5 V-tolerant); default NJTRST after reset (AF0); AF SPI3_MISO/I2S3ext_SD, SPI1_MISO, USART2_RX, TIM3_CH1, TIM16_CH1, TIM17_BKIN, TSC_G5_IO2, EVENTOUT.
41	PB5	bidirectional	GPIO (FT, 5 V-tolerant); AF SPI3_MOSI/I2S3_SD, SPI1_MOSI, I2C1_SMBA, USART2_CK, TIM16_BKIN, TIM3_CH2, TIM17_CH1, EVENTOUT.
42	PB6	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); AF I2C1_SCL, USART1_TX, TIM16_CH1N, TIM4_CH1, TSC_G5_IO3, EVENTOUT.
43	PB7	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); AF I2C1_SDA, USART1_RX, TIM3_CH4, TIM4_CH2, TIM17_CH1N, TSC_G5_IO4, EVENTOUT.
44	BOOT0	input	Dedicated boot mode selection input (0 V to 5.5 V range); sampled at reset: high selects system-memory or SRAM boot per Boot0/Boot1 combination.
45	PB8	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); AF I2C1_SCL, CAN_RX, TIM16_CH1, TIM4_CH3, TIM1_BKIN, TSC_SYNC, COMP1_OUT, EVENTOUT.
46	PB9	bidirectional	GPIO (FTf, 5 V-tolerant, FM+ capable); AF I2C1_SDA, CAN_TX, TIM17_CH1, TIM4_CH4, IR_OUT, COMP2_OUT, EVENTOUT.
47	VSS	power_in	Digital ground; 0 V reference for core logic and I/Os.
48	VDD	power_in	Digital power supply, 2.0 V to 3.6 V, for I/Os and internal voltage regulator.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

CAD (KiCad official)

Symbol: STM32F302CBT6TR
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: stm32f302cbt6tr-etched.step / stm32f302cbt6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f302cbt6tr.step / stm32f302cbt6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (145 pp, sha256 10a072d58aca58c4, retrieved 2026-09-27, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF