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STM32F301C8T6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F301C8T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32F301C8T6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply, 1.65 to 3.6 V, that powers the RTC, the 32 kHz oscillator and the backup registers when VDD is absent.
2 PC13 bidirectional Standard 3.3 V I/O on the backup-domain power switch, limited to 3 mA sink so output use is limited to 2 MHz with 30 pF load and it cannot source LED-type current; also TAMPER1/WKUP2, RTC_TS and RTC_OUT.
3 PC14 bidirectional Standard 3.3 V I/O on the backup-domain power switch with the same limits as PC13; also OSC32_IN for the 32.768 kHz oscillator.
4 PC15 bidirectional Standard 3.3 V I/O on the backup-domain power switch with the same limits as PC13; also OSC32_OUT for the 32.768 kHz oscillator.
5 PF0 bidirectional 5 V tolerant I/O (FTf, with I2C FM+ option) that serves as OSC_IN, the high-speed oscillator input; alternate functions include I2C2_SDA, SPI2_NSS/I2S2_WS and TIM1_CH3N.
6 PF1 output OSC_OUT output of the high-speed oscillator on a 5 V tolerant FTf I/O; alternate functions include I2C2_SCL and SPI2_SCK/I2S2_CK.
7 NRST bidirectional Active-low device reset input and internal reset output with a built-in weak pull-up; the device does not reset if the pin level cannot fall below VIL(NRST) max.
8 VSSA/VREF- power_in Analog ground and negative reference voltage for the ADC, DAC, comparators, op-amp, reset block, RC and PLL.
9 VDDA/VREF+ power_in Analog supply, 2.0 to 3.6 V (2.4 V minimum when DAC or OPAMP are used), and positive reference voltage; VDDA must be at or above VDD and must be powered first.
10 PA0 bidirectional 3.3 V tolerant I/O (TTa) that is also ADC1_IN1, the WKUP1 wakeup pin for Standby, Stop and Sleep modes and RTC_TAMP2; alternate functions include TIM2_CH1/TIM2_ETR, TSC_G1_IO1 and USART2_CTS.
11 PA1 bidirectional 3.3 V tolerant I/O (TTa) that is also ADC1_IN2 and RTC_REFIN; alternate functions include TIM2_CH2, TSC_G1_IO2, USART2_RTS_DE and TIM15_CH1N.
12 PA2 bidirectional 3.3 V tolerant I/O (TTa) that is also ADC1_IN3 and COMP2_INM; alternate functions include TIM2_CH3, TSC_G1_IO3, USART2_TX, COMP2_OUT and TIM15_CH1.
13 PA3 bidirectional 3.3 V tolerant I/O (TTa) that is also ADC1_IN4; alternate functions include TIM2_CH4, TSC_G1_IO4, USART2_RX and TIM15_CH2.
14 PA4 bidirectional 3.3 V tolerant I/O (TTa) with lower touch-sensing sensitivity, recommended for use as a sampling capacitor I/O; also ADC1_IN5, DAC1_OUT1 and COMP2/4/6_INM; alternate functions include TSC_G2_IO1, SPI3_NSS/I2S3_WS and USART2_CK.
15 PA5 bidirectional 3.3 V tolerant I/O (TTa) that is also OPAMP2_VINM; alternate functions include TIM2_CH1/TIM2_ETR and TSC_G2_IO2.
16 PA6 bidirectional 3.3 V tolerant I/O (TTa) with lower touch-sensing sensitivity, recommended for use as a sampling capacitor I/O; also ADC1_IN10 and OPAMP2_VOUT; alternate functions include TIM16_CH1, TSC_G2_IO3 and TIM1_BKIN.
17 PA7 bidirectional 3.3 V tolerant I/O (TTa) that is also ADC1_IN15, COMP2_INP and OPAMP2_VINP; alternate functions include TIM17_CH1, TSC_G2_IO4 and TIM1_CH1N.
18 PB0 bidirectional 3.3 V tolerant I/O (TTa) that is also ADC1_IN11, COMP4_INP and OPAMP2_VINP; alternate functions include TSC_G3_IO2 and TIM1_CH2N.
19 PB1 bidirectional 3.3 V tolerant I/O (TTa) that is also ADC1_IN12; alternate functions include TSC_G3_IO3, TIM1_CH3N and COMP4_OUT.
20 PB2 bidirectional 3.3 V tolerant I/O (TTa) that is also COMP4_INM; alternate function TSC_G3_IO4.
21 PB10 bidirectional Standard 3.3 V I/O (TT); alternate functions include TIM2_CH3, TSC_SYNC and USART3_TX.
22 PB11 bidirectional 3.3 V tolerant I/O (TTa) that is also ADC1_IN14 and COMP6_INP; alternate functions include TIM2_CH4, TSC_G6_IO1 and USART3_RX.
23 VSS_2 power_in Digital ground.
24 VDD_2 power_in Digital supply for I/O and the internal regulator, 2.0 to 3.6 V.
25 PB12 bidirectional Standard 3.3 V I/O (TT); alternate functions include TSC_G6_IO2, I2C2_SMBAL, SPI2_NSS/I2S2_WS, TIM1_BKIN and USART3_CK.
26 PB13 bidirectional 3.3 V tolerant I/O (TTa) that is also ADC1_IN13; alternate functions include TSC_G6_IO3, SPI2_SCK/I2S2_CK, TIM1_CH1N and USART3_CTS.
27 PB14 bidirectional 3.3 V tolerant I/O (TTa) that is also OPAMP2_VINP; alternate functions include TIM15_CH1, TSC_G6_IO4, SPI2_MISO/I2S2ext_SD, TIM1_CH2N and USART3_RTS_DE.
28 PB15 bidirectional 3.3 V tolerant I/O (TTa) that is also COMP6_INM; alternate functions include RTC_REFIN, TIM15_CH2, TIM15_CH1N, TIM1_CH3N and SPI2_MOSI/I2S2_SD.
29 PA8 bidirectional 5 V tolerant I/O (FT); alternate functions include MCO, I2C3_SCL, I2C2_SMBAL, I2S2_MCK, TIM1_CH1 and USART1_CK.
30 PA9 bidirectional 5 V tolerant I/O (FTf, with I2C FM+ option) that is used by the bootloader for USART1 reprogramming; alternate functions include I2C3_SMBAL, TSC_G4_IO1, I2C2_SCL, TIM1_CH2 and USART1_TX.
31 PA10 bidirectional 5 V tolerant I/O (FTf, with I2C FM+ option); alternate functions include TIM17_BKIN, TSC_G4_IO2, I2C2_SDA, SPI2_MISO/I2S2ext_SD, TIM1_CH3, USART1_RX, COMP6_OUT and TIM2_CH4.
32 PA11 bidirectional 5 V tolerant I/O (FT); alternate functions include SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, TIM1_CH4 and TIM1_BKIN2.
33 PA12 bidirectional 5 V tolerant I/O (FT); alternate functions include TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT and TIM1_ETR.
34 PA13 bidirectional 5 V tolerant I/O (FT) that carries SWDIO, the serial-wire debug data line; alternate functions include TIM16_CH1N, TSC_G4_IO3, IR-OUT and USART3_CTS.
35 VSS_3 power_in Digital ground.
36 VDD_3 power_in Digital supply, 2.0 to 3.6 V.
37 PA14 bidirectional 5 V tolerant I/O (FTf, with I2C FM+ option) that carries SWCLK/JTCK, the serial-wire and JTAG clock; alternate functions include TSC_G4_IO4, I2C1_SDA, TIM1_BKIN and USART2_TX.
38 PA15 bidirectional 5 V tolerant I/O (FTf, with I2C FM+ option) that carries JTDI, the JTAG data input; alternate functions include TIM2_CH1/TIM2_ETR, TSC_SYNC, I2C1_SCL, SPI3_NSS/I2S3_WS, USART2_RX and TIM1_BKIN.
39 PB3 bidirectional 5 V tolerant I/O (FT) that carries JTDO/TRACESWO; alternate functions include TIM2_CH2, TSC_G5_IO1, SPI3_SCK/I2S3_CK and USART2_TX.
40 PB4 bidirectional 5 V tolerant I/O (FT) that carries JTRST, the JTAG reset; alternate functions include TIM16_CH1, TSC_G5_IO2, SPI3_MISO/I2S3ext_SD, USART2_RX and TIM17_BKIN.
41 PB5 bidirectional 5 V tolerant I/O (FT); alternate functions include TIM16_BKIN, I2C1_SMBAl, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA and TIM17_CH1.
42 PB6 bidirectional 5 V tolerant I/O (FTf, with I2C FM+ option); alternate functions include TIM16_CH1N, TSC_G5_IO3, I2C1_SCL and USART1_TX.
43 PB7 bidirectional 5 V tolerant I/O (FTf, with I2C FM+ option); alternate functions include TIM17_CH1N, TSC_G5_IO4, I2C1_SDA and USART1_RX.
44 BOOT0 input Boot memory selection input (dedicated BOOT0 pin, 0 to 5.5 V) that, together with the BOOT1 option bit, selects boot from user Flash, system memory or embedded SRAM.
45 PB8 bidirectional 5 V tolerant I/O (FTf, with I2C FM+ option); alternate functions include TIM16_CH1, TSC_SYNC, I2C1_SCL, USART3_RX and TIM1_BKIN.
46 PB9 bidirectional 5 V tolerant I/O (FTf, with I2C FM+ option); alternate functions include TIM17_CH1, I2C1_SDA, IR-OUT, USART3_TX and COMP2_OUT.
47 VSS_1 power_in Digital ground.
48 VDD_1 power_in Digital supply, 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: STM32F301C8T6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f301c8t6-etched.step / stm32f301c8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f301c8t6.step / stm32f301c8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (132 pp, sha256 2d74508ff97e7bf2, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF