component
STM32F205VET6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSTM32F205VET6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
STM32F205VET6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5V-tolerant GPIO; alternate functions TRACECLK, FSMC_A23, ETH_MII_TXD3, EVENTOUT; floating input after reset. |
| 2 | PE3 | bidirectional | 5V-tolerant GPIO; alternate functions TRACED0, FSMC_A19, EVENTOUT; floating input after reset. |
| 3 | PE4 | bidirectional | 5V-tolerant GPIO; alternate functions TRACED1, FSMC_A20, DCMI_D4, EVENTOUT; floating input after reset. |
| 4 | PE5 | bidirectional | 5V-tolerant GPIO; alternate functions TRACED2, FSMC_A21, TIM9_CH1, DCMI_D6, EVENTOUT; floating input after reset. |
| 5 | PE6 | bidirectional | 5V-tolerant GPIO; alternate functions TRACED3, FSMC_A22, TIM9_CH2, DCMI_D7, EVENTOUT; floating input after reset. |
| 6 | VBAT | power_in | Battery supply for RTC, 20×32-bit backup registers, and optional 4 KB backup SRAM; operating range 1.65-3.6 V. |
| 7 | PC13 | bidirectional | 5V-tolerant GPIO supplied through power switch; limited to ≤2 MHz / 30 pF load in output mode; additional function RTC_AF1; EVENTOUT alternate. |
| 8 | PC14 | bidirectional | 5V-tolerant GPIO (not FT in oscillator mode) supplied through power switch; limited to ≤2 MHz / 30 pF; additional function OSC32_IN; EVENTOUT alternate. |
| 9 | PC15 | bidirectional | 5V-tolerant GPIO (not FT in oscillator mode) supplied through power switch; limited to ≤2 MHz / 30 pF; additional function OSC32_OUT; EVENTOUT alternate. |
| 10 | VSS | power_in | Ground reference for digital logic supply domain. |
| 11 | VDD | power_in | Main digital supply voltage; operating range 1.8-3.6 V. |
| 12 | PH0 | bidirectional | 5V-tolerant GPIO (not FT in oscillator mode); additional function OSC_IN (HSE crystal input); EVENTOUT alternate; floating input after reset. |
| 13 | PH1 | bidirectional | 5V-tolerant GPIO (not FT in oscillator mode); additional function OSC_OUT (HSE crystal output); EVENTOUT alternate; floating input after reset. |
| 14 | NRST | bidirectional | Active-low bidirectional reset pin with embedded weak pull-up resistor; VIL(NRST) and VIH(NRST) defined in Table 49. |
| 15 | PC0 | bidirectional | 5V-tolerant GPIO; alternate OTG_HS_ULPI_STP; additional ADC123_IN10 (analog input, max 3.6 V). |
| 16 | PC1 | bidirectional | 5V-tolerant GPIO; alternate ETH_MDC; additional ADC123_IN11. |
| 17 | PC2 | bidirectional | 5V-tolerant GPIO; alternate SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2; additional ADC123_IN12. |
| 18 | PC3 | bidirectional | 5V-tolerant GPIO; alternate SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK; additional ADC123_IN13. |
| 19 | VDD | power_in | Main digital supply voltage; operating range 1.8-3.6 V. |
| 20 | VSSA | power_in | Ground reference for analog supply domain (VDDA/VREF+). |
| 21 | VREF+ | power_in | Positive ADC and DAC reference voltage input; range 1.8 V to VDDA. |
| 22 | VDDA | power_in | Analog supply for ADC, DAC, oscillators, PLL, and internal reference voltage; operating range 1.8-3.6 V. |
| 23 | PA0 | bidirectional | 5V-tolerant GPIO; WKUP pin from Standby; alternate USART2_CTS, UART4_TX, ETH_MII_CRS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR; additional ADC123_IN0, WKUP. |
| 24 | PA1 | bidirectional | 5V-tolerant GPIO; alternate USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, ETH_MII_RX_CLK, TIM5_CH2, TIM2_CH2; additional ADC123_IN1. |
| 25 | PA2 | bidirectional | 5V-tolerant GPIO; alternate USART2_TX, TIM5_CH3, TIM9_CH1, TIM2_CH3, ETH_MDIO; additional ADC123_IN2. |
| 26 | PA3 | bidirectional | 5V-tolerant GPIO; alternate USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0, ETH_MII_COL; additional ADC123_IN3. |
| 27 | VSS | power_in | Ground reference for digital logic supply domain. |
| 28 | VDD | power_in | Main digital supply voltage; operating range 1.8-3.6 V. |
| 29 | PA4 | bidirectional | 3.3V-tolerant (TTa) GPIO; alternate SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF; additional ADC12_IN4, DAC_OUT1. |
| 30 | PA5 | bidirectional | 3.3V-tolerant (TTa) GPIO; alternate SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR, TIM8_CH1N; additional ADC12_IN5, DAC_OUT2. |
| 31 | PA6 | bidirectional | 5V-tolerant GPIO; alternate SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1, TIM1_BKIN; additional ADC12_IN6. |
| 32 | PA7 | bidirectional | 5V-tolerant GPIO; alternate SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV/ETH_RMII_CRS_DV, TIM1_CH1N; additional ADC12_IN7. |
| 33 | PC4 | bidirectional | 5V-tolerant GPIO; alternate ETH_RMII_RXD0, ETH_MII_RXD0; additional ADC12_IN14. |
| 34 | PC5 | bidirectional | 5V-tolerant GPIO; alternate ETH_RMII_RXD1, ETH_MII_RXD1; additional ADC12_IN15. |
| 35 | PB0 | bidirectional | 5V-tolerant GPIO; alternate TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2, TIM1_CH2N; additional ADC12_IN8. |
| 36 | PB1 | bidirectional | 5V-tolerant GPIO; alternate TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3, TIM1_CH3N; additional ADC12_IN9. |
| 37 | PB2 | bidirectional | 5V-tolerant GPIO; also serves as BOOT1 boot-mode selection input after reset; EVENTOUT alternate. |
| 38 | PE7 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D4, TIM1_ETR, EVENTOUT; floating input after reset. |
| 39 | PE8 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D5, TIM1_CH1N, EVENTOUT; floating input after reset. |
| 40 | PE9 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D6, TIM1_CH1, EVENTOUT; floating input after reset. |
| 41 | PE10 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D7, TIM1_CH2N, EVENTOUT; floating input after reset. |
| 42 | PE11 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D8, TIM1_CH2, EVENTOUT; floating input after reset. |
| 43 | PE12 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D9, TIM1_CH3N, EVENTOUT; floating input after reset. |
| 44 | PE13 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D10, TIM1_CH3, EVENTOUT; floating input after reset. |
| 45 | PE14 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D11, TIM1_CH4, EVENTOUT; floating input after reset. |
| 46 | PE15 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D12, TIM1_BKIN, EVENTOUT; floating input after reset. |
| 47 | PB10 | bidirectional | 5V-tolerant GPIO; alternate SPI2_SCK/I2S2_SCK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, TIM2_CH3, EVENTOUT. |
| 48 | PB11 | bidirectional | 5V-tolerant GPIO; alternate I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_RMII_TX_EN/ETH_MII_TX_EN, TIM2_CH4, EVENTOUT. |
| 49 | VCAP_1 | passive | Internal voltage regulator (1.2 V domain) output decoupling node; requires 2.2 µF external capacitor to VSS per Table 16. |
| 50 | VDD | power_in | Main digital supply voltage; operating range 1.8-3.6 V. |
| 51 | PB12 | bidirectional | 5V-tolerant GPIO; alternate SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TXD0, OTG_HS_ID, EVENTOUT. |
| 52 | PB13 | bidirectional | 5V-tolerant GPIO; alternate SPI2_SCK/I2S2_SCK, USART3_CTS, TIM1_CH1N, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TXD1, EVENTOUT; additional OTG_HS_VBUS. |
| 53 | PB14 | bidirectional | 5V-tolerant GPIO; alternate SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM, USART3_RTS, TIM8_CH2N, EVENTOUT. |
| 54 | PB15 | bidirectional | 5V-tolerant GPIO; alternate SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2, OTG_HS_DP, RTC_50Hz, EVENTOUT. |
| 55 | PD8 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D13, USART3_TX, EVENTOUT; floating input after reset. |
| 56 | PD9 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D14, USART3_RX, EVENTOUT; floating input after reset. |
| 57 | PD10 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D15, USART3_CK, EVENTOUT; floating input after reset. |
| 58 | PD11 | bidirectional | 5V-tolerant GPIO; alternate FSMC_A16, USART3_CTS, EVENTOUT; floating input after reset. |
| 59 | PD12 | bidirectional | 5V-tolerant GPIO; alternate FSMC_A17, TIM4_CH1, USART3_RTS, EVENTOUT; floating input after reset. |
| 60 | PD13 | bidirectional | 5V-tolerant GPIO; alternate FSMC_A18, TIM4_CH2, EVENTOUT; floating input after reset. |
| 61 | PD14 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D0, TIM4_CH3, EVENTOUT; floating input after reset. |
| 62 | PD15 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D1, TIM4_CH4, EVENTOUT; floating input after reset. |
| 63 | PC6 | bidirectional | 5V-tolerant GPIO; alternate I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0, TIM3_CH1, EVENTOUT. |
| 64 | PC7 | bidirectional | 5V-tolerant GPIO; alternate I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1, TIM3_CH2, EVENTOUT. |
| 65 | PC8 | bidirectional | 5V-tolerant GPIO; alternate TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK, DCMI_D2, EVENTOUT. |
| 66 | PC9 | bidirectional | 5V-tolerant GPIO; alternate MCO2, I2S2_CKIN, I2S3_CKIN, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3, TIM3_CH4, EVENTOUT. |
| 67 | PA8 | bidirectional | 5V-tolerant GPIO; alternate MCO1, USART1_CK, TIM1_CH1, I2C3_SCL, OTG_FS_SOF, EVENTOUT. |
| 68 | PA9 | bidirectional | 5V-tolerant GPIO; alternate USART1_TX, TIM1_CH2, I2C3_SMBA, DCMI_D0, EVENTOUT; additional OTG_FS_VBUS. |
| 69 | PA10 | bidirectional | 5V-tolerant GPIO; alternate USART1_RX, TIM1_CH3, OTG_FS_ID, DCMI_D1, EVENTOUT. |
| 70 | PA11 | bidirectional | 5V-tolerant GPIO; alternate USART1_CTS, CAN1_RX, TIM1_CH4, OTG_FS_DM, EVENTOUT. |
| 71 | PA12 | bidirectional | 5V-tolerant GPIO; alternate USART1_RTS, CAN1_TX, TIM1_ETR, OTG_FS_DP, EVENTOUT. |
| 72 | PA13 | bidirectional | 5V-tolerant GPIO; default function JTMS-SWDIO (SWD/JTAG debug data); EVENTOUT alternate; floating input after reset. |
| 73 | VCAP_2 | passive | Internal voltage regulator (1.2 V domain) output decoupling node; requires 2.2 µF external capacitor to VSS per Table 16. |
| 74 | VSS | power_in | Ground reference for digital logic supply domain. |
| 75 | VDD | power_in | Main digital supply voltage; operating range 1.8-3.6 V. |
| 76 | PA14 | bidirectional | 5V-tolerant GPIO; default function JTCK-SWCLK (SWD/JTAG debug clock); EVENTOUT alternate. |
| 77 | PA15 | bidirectional | 5V-tolerant GPIO; default function JTDI; alternate SPI3_NSS/I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, EVENTOUT. |
| 78 | PC10 | bidirectional | 5V-tolerant GPIO; alternate SPI3_SCK/I2S3_SCK, UART4_TX, SDIO_D2, DCMI_D8, USART3_TX, EVENTOUT. |
| 79 | PC11 | bidirectional | 5V-tolerant GPIO; alternate UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX, EVENTOUT. |
| 80 | PC12 | bidirectional | 5V-tolerant GPIO; alternate UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI/I2S3_SD, USART3_CK, EVENTOUT. |
| 81 | PD0 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D2, CAN1_RX, EVENTOUT; floating input after reset. |
| 82 | PD1 | bidirectional | 5V-tolerant GPIO; alternate FSMC_D3, CAN1_TX, EVENTOUT; floating input after reset. |
| 83 | PD2 | bidirectional | 5V-tolerant GPIO; alternate TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT. |
| 84 | PD3 | bidirectional | 5V-tolerant GPIO; alternate FSMC_CLK, USART2_CTS, EVENTOUT; floating input after reset. |
| 85 | PD4 | bidirectional | 5V-tolerant GPIO; alternate FSMC_NOE, USART2_RTS, EVENTOUT; floating input after reset. |
| 86 | PD5 | bidirectional | 5V-tolerant GPIO; alternate FSMC_NWE, USART2_TX, EVENTOUT; floating input after reset. |
| 87 | PD6 | bidirectional | 5V-tolerant GPIO; alternate FSMC_NWAIT, USART2_RX, EVENTOUT; floating input after reset. |
| 88 | PD7 | bidirectional | 5V-tolerant GPIO; alternate USART2_CK, FSMC_NE1/FSMC_NCE2, EVENTOUT; floating input after reset. |
| 89 | PB3 | bidirectional | 5V-tolerant GPIO; default function JTDO/TRACESWO; alternate SPI3_SCK/I2S3_SCK, TIM2_CH2, SPI1_SCK, EVENTOUT. |
| 90 | PB4 | bidirectional | 5V-tolerant GPIO; default function NJTRST; alternate SPI3_MISO, TIM3_CH1, SPI1_MISO, EVENTOUT. |
| 91 | PB5 | bidirectional | 5V-tolerant GPIO; alternate I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI/I2S3_SD, DCMI_D10, EVENTOUT. |
| 92 | PB6 | bidirectional | 5V-tolerant GPIO; alternate I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5, USART1_TX, EVENTOUT. |
| 93 | PB7 | bidirectional | 5V-tolerant GPIO; alternate I2C1_SDA, FSMC_NL(NADV), DCMI_VSYNC, USART1_RX, TIM4_CH2, EVENTOUT. |
| 94 | BOOT0 | input | Dedicated BOOT0 pin (type B); selects boot mode together with BOOT1/PB2; accepts VPP programming voltage. |
| 95 | PB8 | bidirectional | 5V-tolerant GPIO; alternate TIM4_CH3, SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL, CAN1_RX, EVENTOUT. |
| 96 | PB9 | bidirectional | 5V-tolerant GPIO; alternate SPI2_NSS/I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA, CAN1_TX, EVENTOUT. |
| 97 | PE0 | bidirectional | 5V-tolerant GPIO; alternate TIM4_ETR, FSMC_NBL0, DCMI_D2, EVENTOUT; floating input after reset. |
| 98 | PE1 | bidirectional | 5V-tolerant GPIO; alternate FSMC_NBL1, DCMI_D3, EVENTOUT; floating input after reset. |
| 99 | RFU | unconnected | Reserved for future use; datasheet states this pin can be tied to VDD, VSS, or left unconnected. |
| 100 | VDD | power_in | Main digital supply voltage; operating range 1.8-3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
STM32F205VET6 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
stm32f205vet6-etched.step/stm32f205vet6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f205vet6.step/stm32f205vet6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (182 pp, sha256
8c96e4bd862cbbb2, retrieved 2026-09-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).