component
STM32F205RGT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F205RGT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32F205RGT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | VBAT supply input to backup domain, 1.8 to 3.6 V for RTC, backup registers, and optional backup SRAM. |
| 2 | PC13 | bidirectional | GPIO PC13, 5V-tolerant I/O with RTC backup domain function. |
| 3 | PC14/OSC32_IN | bidirectional | GPIO PC14, 5V-tolerant I/O, can be configured as 32 kHz oscillator input. |
| 4 | PC15/OSC32_OUT | bidirectional | GPIO PC15, 5V-tolerant I/O, can be configured as 32 kHz oscillator output. |
| 5 | PH0/OSC_IN | bidirectional | GPIO PH0, 5V-tolerant I/O, can be configured as 4-26 MHz external oscillator input. |
| 6 | PH1/OSC_OUT | bidirectional | GPIO PH1, 5V-tolerant I/O, can be configured as 4-26 MHz external oscillator output. |
| 7 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor, active low. |
| 8 | PC0 | bidirectional | GPIO PC0, 5V-tolerant I/O with ADC123 channel 10 input capability. |
| 9 | PC1 | bidirectional | GPIO PC1, 5V-tolerant I/O with ADC123 channel 11 input capability. |
| 10 | PC2 | bidirectional | GPIO PC2, 5V-tolerant I/O with ADC123 channel 12 input capability. |
| 11 | PC3 | bidirectional | GPIO PC3, 5V-tolerant I/O with ADC123 channel 13 input capability. |
| 12 | VSSA | power_in | Analog ground for ADC and DAC, 0 V reference for analog circuits. |
| 13 | VDDA | power_in | Analog power supply input, 1.8 to 3.6 V for ADC, DAC, and comparators. |
| 14 | PA0-WKUP | bidirectional | GPIO PA0, 5V-tolerant I/O with wakeup and ADC123 channel 0 input capability. |
| 15 | PA1 | bidirectional | GPIO PA1, 5V-tolerant I/O with ADC123 channel 1 input capability. |
| 16 | PA2 | bidirectional | GPIO PA2, 5V-tolerant I/O with ADC123 channel 2 input capability. |
| 17 | PA3 | bidirectional | GPIO PA3, 5V-tolerant I/O with ADC123 channel 3 input capability. |
| 18 | VSS | power_in | Digital ground supply, 0 V reference for digital circuits. |
| 19 | VDD | power_in | Main power supply input, 1.8 to 3.6 V for core, I/O, and peripherals. |
| 20 | PA4 | bidirectional | GPIO PA4, 3.3V-tolerant I/O with ADC12 channel 4 input and DAC_OUT1 capability. |
| 21 | PA5 | bidirectional | GPIO PA5, 3.3V-tolerant I/O with ADC12 channel 5 input and DAC_OUT2 capability. |
| 22 | PA6 | bidirectional | GPIO PA6, 5V-tolerant I/O with ADC12 channel 6 input capability. |
| 23 | PA7 | bidirectional | GPIO PA7, 5V-tolerant I/O with ADC12 channel 7 input capability. |
| 24 | PC4 | bidirectional | GPIO PC4, 5V-tolerant I/O with ADC12 channel 14 input capability. |
| 25 | PC5 | bidirectional | GPIO PC5, 5V-tolerant I/O with ADC12 channel 15 input capability. |
| 26 | PB0 | bidirectional | GPIO PB0, 5V-tolerant I/O with ADC12 channel 8 input capability. |
| 27 | PB1 | bidirectional | GPIO PB1, 5V-tolerant I/O with ADC12 channel 9 input capability. |
| 28 | PB2/BOOT1 | bidirectional | GPIO PB2, 5V-tolerant I/O, boot configuration pin affecting system startup. |
| 29 | PB10 | bidirectional | GPIO PB10, 5V-tolerant I/O with SPI2/I2C2 alternate functions. |
| 30 | PB11 | bidirectional | GPIO PB11, 5V-tolerant I/O with I2C2/USART3 alternate functions. |
| 31 | VCAP_1 | passive | External capacitor connection (2.2 µF) for internal voltage regulator stabilization. |
| 32 | VDD | power_in | Main power supply input, 1.8 to 3.6 V for core, I/O, and peripherals. |
| 33 | PB12 | bidirectional | GPIO PB12, 5V-tolerant I/O with SPI2/I2C2/CAN2 alternate functions. |
| 34 | PB13 | bidirectional | GPIO PB13, 5V-tolerant I/O with SPI2/CAN2/OTG_HS_VBUS alternate functions. |
| 35 | PB14 | bidirectional | GPIO PB14, 5V-tolerant I/O with SPI2/TIM1/OTG_HS_DM alternate functions. |
| 36 | PB15 | bidirectional | GPIO PB15, 5V-tolerant I/O with SPI2/I2S2/TIM1/OTG_HS_DP alternate functions. |
| 37 | PC6 | bidirectional | GPIO PC6, 5V-tolerant I/O with I2S2/TIM8/SDIO/USART6 alternate functions. |
| 38 | PC7 | bidirectional | GPIO PC7, 5V-tolerant I/O with I2S3/TIM8/SDIO/USART6 alternate functions. |
| 39 | PC8 | bidirectional | GPIO PC8, 5V-tolerant I/O with TIM8/SDIO/USART6 alternate functions. |
| 40 | PC9 | bidirectional | GPIO PC9, 5V-tolerant I/O with MCO2/I2S2/I2S3/TIM8/SDIO alternate functions. |
| 41 | PA8 | bidirectional | GPIO PA8, 5V-tolerant I/O with MCO1/USART1/TIM1/I2C3 alternate functions. |
| 42 | PA9 | bidirectional | GPIO PA9, 5V-tolerant I/O with OTG_FS_VBUS/USART1/TIM1 alternate functions. |
| 43 | PA10 | bidirectional | GPIO PA10, 5V-tolerant I/O with OTG_FS_ID/USART1/TIM1 alternate functions. |
| 44 | PA11 | bidirectional | GPIO PA11, 5V-tolerant I/O with OTG_FS_DM/USART1/CAN1 alternate functions. |
| 45 | PA12 | bidirectional | GPIO PA12, 5V-tolerant I/O with OTG_FS_DP/USART1/CAN1 alternate functions. |
| 46 | PA13 | bidirectional | GPIO PA13, 5V-tolerant I/O, JTAG test mode select and SWD I/O debug pin. |
| 47 | VCAP_2 | passive | External capacitor connection (2.2 µF) for internal voltage regulator stabilization. |
| 48 | VDD | power_in | Main power supply input, 1.8 to 3.6 V for core, I/O, and peripherals. |
| 49 | PA14 | bidirectional | GPIO PA14, 5V-tolerant I/O, JTAG test clock and SWD clock debug pin. |
| 50 | PA15 | bidirectional | GPIO PA15, 5V-tolerant I/O, JTAG test data input debug pin. |
| 51 | PC10 | bidirectional | GPIO PC10, 5V-tolerant I/O with SPI3/I2S3/UART4/SDIO/USART3 alternate functions. |
| 52 | PC11 | bidirectional | GPIO PC11, 5V-tolerant I/O with SPI3/UART4/SDIO/USART3 alternate functions. |
| 53 | PC12 | bidirectional | GPIO PC12, 5V-tolerant I/O with SPI3/I2S3/UART5/SDIO/USART3 alternate functions. |
| 54 | PD2 | bidirectional | GPIO PD2, 5V-tolerant I/O with TIM3/UART5/SDIO alternate functions. |
| 55 | PB3 | bidirectional | GPIO PB3, 5V-tolerant I/O, JTAG test data output and ETM trace SWO debug pin. |
| 56 | PB4 | bidirectional | GPIO PB4, 5V-tolerant I/O with SPI1/SPI3/TIM3 alternate functions. |
| 57 | PB5 | bidirectional | GPIO PB5, 5V-tolerant I/O with I2C1/SPI1/SPI3/I2S3/CAN2 alternate functions. |
| 58 | PB6 | bidirectional | GPIO PB6, 5V-tolerant I/O with I2C1/TIM4/CAN2/USART1 alternate functions. |
| 59 | PB7 | bidirectional | GPIO PB7, 5V-tolerant I/O with I2C1/TIM4/USART1/FSMC alternate functions. |
| 60 | BOOT0 | input | Boot pin: high selects execution from user Flash memory, low selects system bootloader. |
| 61 | PB8 | bidirectional | GPIO PB8, 5V-tolerant I/O with TIM4/TIM10/SDIO/I2C1/CAN1 alternate functions. |
| 62 | PB9 | bidirectional | GPIO PB9, 5V-tolerant I/O with SPI2/I2S2/TIM4/TIM11/SDIO/I2C1/CAN1 alternate functions. |
| 63 | VSS | power_in | Digital ground supply, 0 V reference for digital circuits. |
| 64 | VDD | power_in | Main power supply input, 1.8 to 3.6 V for core, I/O, and peripherals. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32F205RGT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32f205rgt6-etched.step/stm32f205rgt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f205rgt6.step/stm32f205rgt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (179 pp, sha256
6ffebd41462b5c10, retrieved 2026-09-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).