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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM32F205RET7

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F205RET7 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Backup-domain supply for the RTC, the 20 x 32-bit backup registers and the optional 4 Kbyte backup SRAM.
2	PC13-RTC_AF1	bidirectional	5 V-tolerant I/O supplied through the power switch, limited to 3 mA sink, so output speed must stay at or below 2 MHz with 30 pF load and it must not source current such as an LED.
3	PC14-OSC32_IN	bidirectional	5 V-tolerant I/O supplied through the power switch (3 mA limit, 2 MHz / 30 pF output limit), also serving as the OSC32_IN low-speed oscillator input.
4	PC15-OSC32_OUT	bidirectional	5 V-tolerant I/O supplied through the power switch (3 mA limit, 2 MHz / 30 pF output limit), also serving as the OSC32_OUT low-speed oscillator output.
5	PH0-OSC_IN	bidirectional	5 V-tolerant I/O (FT) except in oscillator mode, where it serves as the OSC_IN high-speed oscillator input.
6	PH1-OSC_OUT	bidirectional	5 V-tolerant I/O (FT) except in oscillator mode, where it serves as the OSC_OUT high-speed oscillator output.
7	NRST	bidirectional	Bidirectional reset pin with an embedded weak pull-up resistor.
8	PC0	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC123_IN10 analog input and OTG_HS_ULPI_STP alternate function.
9	PC1	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC123_IN11 analog input and ETH_MDC alternate function.
10	PC2	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC123_IN12 analog input and SPI2_MISO alternate function.
11	PC3	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC123_IN13 analog input and SPI2_MOSI alternate function.
12	VSSA	power_in	Analog ground pin; the extracted pages give no further limit for it.
13	VDDA	power_in	Analog supply pin; the extracted pages give no voltage limit for it.
14	PA0-WKUP	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC123_IN0 analog input and WKUP wake-up function.
15	PA1	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC123_IN1 analog input and USART2_RTS alternate function.
16	PA2	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC123_IN2 analog input and USART2_TX alternate function.
17	PA3	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC123_IN3 analog input and USART2_RX alternate function.
18	VSS	power_in	Ground reference pin for the digital core and I/Os.
19	VDD	power_in	Digital and I/O supply; the features list gives the application supply and I/O range as 1.8 to 3.6 V.
20	PA4	bidirectional	3.3 V-tolerant I/O (TTa) with ADC12_IN4 and DAC_OUT1 analog functions and SPI1_NSS alternate function.
21	PA5	bidirectional	3.3 V-tolerant I/O (TTa) with ADC12_IN5 and DAC_OUT2 analog functions and SPI1_SCK alternate function.
22	PA6	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC12_IN6 analog input and SPI1_MISO alternate function.
23	PA7	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC12_IN7 analog input and SPI1_MOSI alternate function.
24	PC4	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC12_IN14 analog input and ETH_RMII_RXD0 alternate function.
25	PC5	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC12_IN15 analog input and ETH_RMII_RXD1 alternate function.
26	PB0	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC12_IN8 analog input and TIM3_CH3 alternate function.
27	PB1	bidirectional	5 V-tolerant I/O (FT, except in analog mode) with ADC12_IN9 analog input and TIM3_CH4 alternate function.
28	PB2/BOOT1	bidirectional	5 V-tolerant I/O (FT); Table 8 lists only EVENTOUT as its alternate function and names the pin PB2/BOOT1.
29	PB10	bidirectional	5 V-tolerant I/O (FT) with SPI2_SCK, I2S2_SCK, I2C2_SCL and USART3_TX alternate functions.
30	PB11	bidirectional	5 V-tolerant I/O (FT) with I2C2_SDA, USART3_RX and ETH_MII_TX_EN alternate functions.
31	VCAP_1	power_in	Internal voltage regulator decoupling pin; the required external capacitor is specified in Section 6.3.2, which is not in the extracted text.
32	VDD	power_in	Digital and I/O supply; the features list gives the application supply and I/O range as 1.8 to 3.6 V.
33	PB12	bidirectional	5 V-tolerant I/O (FT) with SPI2_NSS, I2S2_WS, CAN2_RX and OTG_HS_ID alternate functions.
34	PB13	bidirectional	5 V-tolerant I/O (FT) with SPI2_SCK, USART3_CTS, CAN2_TX and OTG_HS_VBUS as additional function.
35	PB14	bidirectional	5 V-tolerant I/O (FT) with SPI2_MISO, TIM12_CH1 and OTG_HS_DM alternate functions.
36	PB15	bidirectional	5 V-tolerant I/O (FT) with SPI2_MOSI, I2S2_SD, TIM12_CH2, OTG_HS_DP and RTC_50Hz alternate functions.
37	PC6	bidirectional	5 V-tolerant I/O (FT) with I2S2_MCK, TIM8_CH1, SDIO_D6 and USART6_TX alternate functions.
38	PC7	bidirectional	5 V-tolerant I/O (FT) with I2S3_MCK, TIM8_CH2, SDIO_D7 and USART6_RX alternate functions.
39	PC8	bidirectional	5 V-tolerant I/O (FT) with TIM8_CH3, SDIO_D0, TIM3_CH3 and USART6_CK alternate functions.
40	PC9	bidirectional	5 V-tolerant I/O (FT) with MCO2, TIM8_CH4, SDIO_D1, I2C3_SDA and DCMI_D3 alternate functions.
41	PA8	bidirectional	5 V-tolerant I/O (FT) with MCO1, TIM1_CH1, I2C3_SCL, USART1_CK and OTG_FS_SOF alternate functions.
42	PA9	bidirectional	5 V-tolerant I/O (FT) with USART1_TX, TIM1_CH2, I2C3_SMBA and DCMI_D0 alternate functions and OTG_FS_VBUS as additional function.
43	PA10	bidirectional	5 V-tolerant I/O (FT) with USART1_RX, TIM1_CH3, OTG_FS_ID and DCMI_D1 alternate functions.
44	PA11	bidirectional	5 V-tolerant I/O (FT) with USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM alternate functions.
45	PA12	bidirectional	5 V-tolerant I/O (FT) with USART1_RTS, CAN1_TX, TIM1_ETR and OTG_FS_DP alternate functions.
46	PA13	bidirectional	5 V-tolerant I/O (FT) carrying the JTMS-SWDIO serial-wire debug function.
47	VCAP_2	power_in	Internal voltage regulator decoupling pin; the required external capacitor is specified in Section 6.3.2, which is not in the extracted text.
48	VDD	power_in	Digital and I/O supply; the features list gives the application supply and I/O range as 1.8 to 3.6 V.
49	PA14	bidirectional	5 V-tolerant I/O (FT) carrying the JTCK-SWCLK serial-wire debug function.
50	PA15 (JTDI)	bidirectional	5 V-tolerant I/O (FT) carrying the JTDI debug function, with SPI1_NSS, SPI3_NSS, I2S3_WS and TIM2_CH1_ETR alternate functions.
51	PC10	bidirectional	5 V-tolerant I/O (FT) with SPI3_SCK, I2S3_SCK, UART4_TX, SDIO_D2 and USART3_TX alternate functions.
52	PC11	bidirectional	5 V-tolerant I/O (FT) with UART4_RX, SPI3_MISO, SDIO_D3 and USART3_RX alternate functions.
53	PC12	bidirectional	5 V-tolerant I/O (FT) with UART5_TX, SDIO_CK, SPI3_MOSI, I2S3_SD and USART3_CK alternate functions.
54	PD2	bidirectional	5 V-tolerant I/O (FT) with TIM3_ETR, UART5_RX, SDIO_CMD and DCMI_D11 alternate functions.
55	PB3	bidirectional	5 V-tolerant I/O (FT) carrying the JTDO/TRACESWO debug function, with SPI3_SCK, I2S3_SCK, TIM2_CH2 and SPI1_SCK alternate functions.
56	PB4	bidirectional	5 V-tolerant I/O (FT) with the NJTRST debug reset alternate function, plus SPI3_MISO, TIM3_CH1 and SPI1_MISO.
57	PB5	bidirectional	5 V-tolerant I/O (FT) with I2C1_SMBA, CAN2_RX, TIM3_CH2, SPI1_MOSI and DCMI_D10 alternate functions.
58	PB6	bidirectional	5 V-tolerant I/O (FT) with I2C1_SCL, TIM4_CH1, CAN2_TX, USART1_TX and DCMI_D5 alternate functions.
59	PB7	bidirectional	5 V-tolerant I/O (FT) with I2C1_SDA, FSMC_NL, DCMI_VSYNC, USART1_RX and TIM4_CH2 alternate functions.
60	BOOT0	input	Dedicated BOOT0 input-only pin, also listed as VPP for Flash programming.
61	PB8	bidirectional	5 V-tolerant I/O (FT) with TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, SDIO_D4 and DCMI_D6 alternate functions.
62	PB9	bidirectional	5 V-tolerant I/O (FT) with SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, I2C1_SDA, CAN1_TX, SDIO_D5 and DCMI_D7 alternate functions.
63	VSS	power_in	Ground reference pin for the digital core and I/Os.
64	VDD	power_in	Digital and I/O supply; the features list gives the application supply and I/O range as 1.8 to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

CAD (KiCad official)

Symbol: STM32F205RET7
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: stm32f205ret7-etched.step / stm32f205ret7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f205ret7.step / stm32f205ret7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (181 pp, sha256 774f5ff3acf8fdf5, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF