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STM32F107VCT7

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F107VCT7

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F107VCT7 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant (FT) I/O PE2 with alternate function TRACECK.
2 PE3 bidirectional 5 V-tolerant (FT) I/O PE3 with alternate function TRACED0.
3 PE4 bidirectional 5 V-tolerant (FT) I/O PE4 with alternate function TRACED1.
4 PE5 bidirectional 5 V-tolerant (FT) I/O PE5 with alternate function TRACED2.
5 PE6 bidirectional 5 V-tolerant (FT) I/O PE6 with alternate function TRACED3.
6 VBAT power_in Power supply for the RTC, the 32 kHz oscillator and backup registers when VDD is not present, 1.8 to 3.6 V.
7 PC13-TAMPER-RTC bidirectional I/O PC13 (TAMPER-RTC alternate function) supplied through the power switch, so output use is limited to 2 MHz mode with at most 30 pF load and only one such pin in output mode at a time.
8 PC14-OSC32_IN bidirectional I/O PC14 (OSC32_IN alternate function) supplied through the power switch, so output use is limited to 2 MHz mode with at most 30 pF load and only one such pin in output mode at a time.
9 PC15-OSC32_OUT bidirectional I/O PC15 (OSC32_OUT alternate function) supplied through the power switch, so output use is limited to 2 MHz mode with at most 30 pF load and only one such pin in output mode at a time.
10 VSS_5 power_in Digital ground pin.
11 VDD_5 power_in Digital supply for I/Os and the internal regulator, 2.0 to 3.6 V.
12 OSC_IN input External oscillator input for the 3 to 25 MHz HSE clock.
13 OSC_OUT output External oscillator output for the 3 to 25 MHz HSE crystal.
14 NRST bidirectional Device reset pin (listed as I/O in Table 5); the excerpt gives no polarity or threshold details.
15 PC0 bidirectional I/O PC0 with ADC12_IN10 analog input.
16 PC1 bidirectional I/O PC1 with ADC12_IN11 analog input; alternate ETH_MII_MDC/ETH_RMII_MDC.
17 PC2 bidirectional I/O PC2 with ADC12_IN12 analog input; alternate ETH_MII_TXD2.
18 PC3 bidirectional I/O PC3 with ADC12_IN13 analog input; alternate ETH_MII_TX_CLK.
19 VSSA power_in Analog ground for the ADC, reset blocks, RCs and PLL; must be connected to VSS.
20 VREF- power_in Negative voltage reference pin listed as a supply in Table 5; the excerpt gives no further limits.
21 VREF+ power_in Positive voltage reference input; the DAC uses VREF+ as its input voltage reference.
22 VDDA power_in Analog supply for ADC, reset blocks, RCs and PLL, 2.0 to 3.6 V, minimum 2.4 V when the ADC is used; must be connected to VDD.
23 PA0-WKUP bidirectional I/O PA0 with WKUP wake-up function, ADC12_IN0 analog input, and alternates TIM2_CH1_ETR, TIM5_CH1, ETH_MII_CRS_WKUP and USART2_CTS (remappable).
24 PA1 bidirectional I/O PA1 with ADC12_IN1 analog input; alternates USART2_RTS, TIM5_CH2, TIM2_CH2, ETH_MII_RX_CLK/ETH_RMII_REF_CLK.
25 PA2 bidirectional I/O PA2 with ADC12_IN2 analog input; alternates USART2_TX, TIM5_CH3, TIM2_CH3, ETH_MII_MDIO/ETH_RMII_MDIO.
26 PA3 bidirectional I/O PA3 with ADC12_IN3 analog input; alternates USART2_RX, TIM5_CH4, TIM2_CH4, ETH_MII_COL.
27 VSS_4 power_in Digital ground pin.
28 VDD_4 power_in Digital supply for I/Os and the internal regulator, 2.0 to 3.6 V.
29 PA4 bidirectional I/O PA4 with DAC_OUT1 and ADC12_IN4; alternates SPI1_NSS and USART2_CK, with SPI3_NSS/I2S3_WS as remap.
30 PA5 bidirectional I/O PA5 with DAC_OUT2 and ADC12_IN5; alternate SPI1_SCK.
31 PA6 bidirectional I/O PA6 with ADC12_IN6; alternates SPI1_MISO, TIM3_CH1 and TIM1_BKIN.
32 PA7 bidirectional I/O PA7 with ADC12_IN7; alternates SPI1_MOSI, TIM3_CH2, TIM1_CH1N, ETH_MII_RX_DV/ETH_RMII_CRS_DV.
33 PC4 bidirectional I/O PC4 with ADC12_IN14 analog input; alternate ETH_MII_RXD0/ETH_RMII_RXD0.
34 PC5 bidirectional I/O PC5 with ADC12_IN15 analog input; alternate ETH_MII_RXD1/ETH_RMII_RXD1.
35 PB0 bidirectional I/O PB0 with ADC12_IN8 analog input; alternates TIM3_CH3, TIM1_CH2N and ETH_MII_RXD2.
36 PB1 bidirectional I/O PB1 with ADC12_IN9 analog input; alternates TIM3_CH4, TIM1_CH3N and ETH_MII_RXD3.
37 PB2/BOOT1 bidirectional 5 V-tolerant (FT) I/O PB2, shared with the BOOT1 boot-option pin.
38 PE7 bidirectional 5 V-tolerant (FT) I/O PE7 with alternate function TIM1_ETR.
39 PE8 bidirectional 5 V-tolerant (FT) I/O PE8 with alternate function TIM1_CH1N.
40 PE9 bidirectional 5 V-tolerant (FT) I/O PE9 with alternate function TIM1_CH1.
41 PE10 bidirectional 5 V-tolerant (FT) I/O PE10 with alternate function TIM1_CH2N.
42 PE11 bidirectional 5 V-tolerant (FT) I/O PE11 with alternate function TIM1_CH2.
43 PE12 bidirectional 5 V-tolerant (FT) I/O PE12 with alternate function TIM1_CH3N.
44 PE13 bidirectional 5 V-tolerant (FT) I/O PE13 with alternate function TIM1_CH3.
45 PE14 bidirectional 5 V-tolerant (FT) I/O PE14 with alternate function TIM1_CH4.
46 PE15 bidirectional 5 V-tolerant (FT) I/O PE15 with alternate function TIM1_BKIN.
47 PB10 bidirectional 5 V-tolerant (FT) I/O PB10; alternates I2C2_SCL, USART3_TX, ETH_MII_RX_ER and TIM2_CH3 (I2C2 not available when Ethernet is used).
48 PB11 bidirectional 5 V-tolerant (FT) I/O PB11; alternates I2C2_SDA, USART3_RX, ETH_MII_TX_EN/ETH_RMII_TX_EN and TIM2_CH4.
49 VSS_1 power_in Digital ground pin.
50 VDD_1 power_in Digital supply for I/Os and the internal regulator, 2.0 to 3.6 V.
51 PB12 bidirectional 5 V-tolerant (FT) I/O PB12; alternates SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX and ETH_MII_TXD0/ETH_RMII_TXD0.
52 PB13 bidirectional 5 V-tolerant (FT) I/O PB13; alternates SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and ETH_MII_TXD1/ETH_RMII_TXD1.
53 PB14 bidirectional 5 V-tolerant (FT) I/O PB14; alternates SPI2_MISO, TIM1_CH2N and USART3_RTS.
54 PB15 bidirectional 5 V-tolerant (FT) I/O PB15; alternates SPI2_MOSI/I2S2_SD and TIM1_CH3N.
55 PD8 bidirectional 5 V-tolerant (FT) I/O PD8; alternates USART3_TX and ETH_MII_RX_DV/ETH_RMII_CRS_DV.
56 PD9 bidirectional 5 V-tolerant (FT) I/O PD9; alternates USART3_RX and ETH_MII_RXD0/ETH_RMII_RXD0.
57 PD10 bidirectional 5 V-tolerant (FT) I/O PD10; alternates USART3_CK and ETH_MII_RXD1/ETH_RMII_RXD1.
58 PD11 bidirectional 5 V-tolerant (FT) I/O PD11; alternates USART3_CTS and ETH_MII_RXD2.
59 PD12 bidirectional 5 V-tolerant (FT) I/O PD12; alternates TIM4_CH1, USART3_RTS and ETH_MII_RXD3.
60 PD13 bidirectional 5 V-tolerant (FT) I/O PD13 with alternate function TIM4_CH2.
61 PD14 bidirectional 5 V-tolerant (FT) I/O PD14 with alternate function TIM4_CH3.
62 PD15 bidirectional 5 V-tolerant (FT) I/O PD15 with alternate function TIM4_CH4.
63 PC6 bidirectional 5 V-tolerant (FT) I/O PC6; alternates I2S2_MCK and TIM3_CH1.
64 PC7 bidirectional 5 V-tolerant (FT) I/O PC7; alternates I2S3_MCK and TIM3_CH2.
65 PC8 bidirectional 5 V-tolerant (FT) I/O PC8 with alternate function TIM3_CH3.
66 PC9 bidirectional 5 V-tolerant (FT) I/O PC9 with alternate function TIM3_CH4.
67 PA8 bidirectional 5 V-tolerant (FT) I/O PA8; alternates USART1_CK, OTG_FS_SOF, TIM1_CH1 and MCO.
68 PA9 bidirectional 5 V-tolerant (FT) I/O PA9; alternates USART1_TX, TIM1_CH2 and OTG_FS_VBUS.
69 PA10 bidirectional 5 V-tolerant (FT) I/O PA10; alternates USART1_RX, TIM1_CH3 and OTG_FS_ID.
70 PA11 bidirectional 5 V-tolerant (FT) I/O PA11; alternates USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM.
71 PA12 bidirectional 5 V-tolerant (FT) I/O PA12; alternates USART1_RTS, OTG_FS_DP, CAN1_TX and TIM1_ETR.
72 PA13 bidirectional 5 V-tolerant (FT) I/O; after reset the pin carries the JTMS-SWDIO debug function.
73 NC unconnected Not connected pin on the LQFP100 package, per Table 5.
74 VSS_2 power_in Digital ground pin.
75 VDD_2 power_in Digital supply for I/Os and the internal regulator, 2.0 to 3.6 V.
76 PA14 bidirectional 5 V-tolerant (FT) I/O; after reset the pin carries the JTCK-SWCLK debug function.
77 PA15 bidirectional 5 V-tolerant (FT) I/O; after reset the pin carries the JTDI debug function, with alternates SPI3_NSS/I2S3_WS, TIM2_CH1_ETR and SPI1_NSS (remap).
78 PC10 bidirectional 5 V-tolerant (FT) I/O PC10; alternates UART4_TX, USART3_TX and SPI3_SCK/I2S3_CK.
79 PC11 bidirectional 5 V-tolerant (FT) I/O PC11; alternates UART4_RX, USART3_RX and SPI3_MISO.
80 PC12 bidirectional 5 V-tolerant (FT) I/O PC12; alternates UART5_TX, USART3_CK and SPI3_MOSI/I2S3_SD.
81 PD0 bidirectional 5 V-tolerant (FT) I/O PD0, available by default on LQFP100; alternates OSC_IN (Table 5 note 9) and CAN1_RX.
82 PD1 bidirectional 5 V-tolerant (FT) I/O PD1, available by default on LQFP100; alternates OSC_OUT (Table 5 note 9) and CAN1_TX.
83 PD2 bidirectional 5 V-tolerant (FT) I/O PD2; alternates TIM3_ETR and UART5_RX.
84 PD3 bidirectional 5 V-tolerant (FT) I/O PD3 with alternate function USART2_CTS.
85 PD4 bidirectional 5 V-tolerant (FT) I/O PD4 with alternate function USART2_RTS.
86 PD5 bidirectional 5 V-tolerant (FT) I/O PD5 with alternate function USART2_TX.
87 PD6 bidirectional 5 V-tolerant (FT) I/O PD6 with alternate function USART2_RX.
88 PD7 bidirectional 5 V-tolerant (FT) I/O PD7 with alternate function USART2_CK.
89 PB3 bidirectional 5 V-tolerant (FT) I/O; after reset the pin carries the JTDO debug function, with alternates SPI3_SCK/I2S3_CK, TRACESWO, TIM2_CH2 and SPI1_SCK.
90 PB4 bidirectional 5 V-tolerant (FT) I/O; after reset the pin carries the NJTRST debug function, with alternates SPI3_MISO, TIM3_CH1 and SPI1_MISO.
91 PB5 bidirectional I/O PB5 (not 5 V-tolerant per Table 5); alternates I2C1_SMBA, SPI3_MOSI/I2S3_SD, ETH_MII_PPS_OUT, TIM3_CH2, SPI1_MOSI and CAN2_RX.
92 PB6 bidirectional 5 V-tolerant (FT) I/O PB6; alternates I2C1_SCL, TIM4_CH1, USART1_TX and CAN2_TX.
93 PB7 bidirectional 5 V-tolerant (FT) I/O PB7; alternates I2C1_SDA, TIM4_CH2 and USART1_RX.
94 BOOT0 input Boot-mode selection pin sampled at startup to choose user Flash, system memory or embedded SRAM boot.
95 PB8 bidirectional 5 V-tolerant (FT) I/O PB8; alternates TIM4_CH3, ETH_MII_TXD3, I2C1_SCL and CAN1_RX.
96 PB9 bidirectional 5 V-tolerant (FT) I/O PB9; alternates TIM4_CH4, I2C1_SDA and CAN1_TX.
97 PE0 bidirectional 5 V-tolerant (FT) I/O PE0 with alternate function TIM4_ETR.
98 PE1 bidirectional 5 V-tolerant (FT) I/O PE1 with no alternate function listed in Table 5.
99 VSS_3 power_in Digital ground pin.
100 VDD_3 power_in Digital supply for I/Os and the internal regulator, 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F107VCT7
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f107vct7-etched.step / stm32f107vct7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f107vct7.step / stm32f107vct7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (108 pp, sha256 ca4bad652e5eb36d, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF