Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

STM32F107VCT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F107VCT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO port E pin 2 with 5V tolerance and trace clock (TRACECK) alternate function capability.
2 PE3 bidirectional GPIO port E pin 3 with 5V tolerance and trace data 0 (TRACED0) alternate function capability.
3 PE4 bidirectional GPIO port E pin 4 with 5V tolerance and trace data 1 (TRACED1) alternate function capability.
4 PE5 bidirectional GPIO port E pin 5 with 5V tolerance and trace data 2 (TRACED2) alternate function capability.
5 PE6 bidirectional GPIO port E pin 6 with 5V tolerance and trace data 3 (TRACED3) alternate function capability.
6 VBAT power_in Backup battery supply (1.8 V to 3.6 V) for RTC, oscillator, and backup registers when VDD is absent.
7 PC13-TAMPER-RTC bidirectional Backup domain I/O with tamper detection and RTC alarm output capability.
8 PC14-OSC32_IN bidirectional 32 kHz oscillator input pin for low-speed external clock.
9 PC15-OSC32_OUT bidirectional 32 kHz oscillator output pin for low-speed external clock.
10 VSS_5 power_in Ground supply pin 5.
11 VDD_5 power_in Main digital power supply pin 5 (2.0 V to 3.6 V).
12 OSC_IN input Main oscillator input for 3 MHz to 25 MHz external crystal or clock.
13 OSC_OUT output Main oscillator output connecting to external crystal.
14 NRST bidirectional External reset pin with internal pull-up resistor and Schmitt trigger input.
15 PC0 bidirectional GPIO port C pin 0 with ADC channel 10 input capability.
16 PC1 bidirectional GPIO port C pin 1 with ADC channel 11 input, Ethernet MDC clock, and RMII MDC alternate functions.
17 PC2 bidirectional GPIO port C pin 2 with ADC channel 12 input and Ethernet MII transmit data 2 alternate function.
18 PC3 bidirectional GPIO port C pin 3 with ADC channel 13 input and Ethernet MII transmit clock alternate function.
19 VSSA power_in Analog ground supply pin.
20 VREF- power_in Negative analog reference voltage input for ADC/DAC (typically connected to VSSA).
21 VREF+ power_in Positive analog reference voltage input for ADC/DAC (typically connected to VDDA).
22 VDDA power_in Analog power supply (2.4 V to 3.6 V when ADC is used, must be connected to VDD).
23 PA0-WKUP bidirectional GPIO port A pin 0 with wakeup from Standby capability, USART2 CTS, ADC channel 0, and Ethernet alternate functions.
24 PA1 bidirectional GPIO port A pin 1 with USART2 RTS, ADC channel 1, timer channels, and Ethernet MII/RMII reference clock alternate functions.
25 PA2 bidirectional GPIO port A pin 2 with USART2 TX, timer channels, ADC channel 2, and Ethernet MDIO alternate functions.
26 PA3 bidirectional GPIO port A pin 3 with USART2 RX, timer channels, ADC channel 3, and Ethernet COL alternate functions.
27 VSS_4 power_in Ground supply pin 4.
28 VDD_4 power_in Main digital power supply pin 4 (2.0 V to 3.6 V).
29 PA4 bidirectional GPIO port A pin 4 with SPI1 NSS, DAC output 1, USART2 clock, and ADC channel 4 alternate functions.
30 PA5 bidirectional GPIO port A pin 5 with SPI1 clock, DAC output 2, and ADC channel 5 alternate functions.
31 PA6 bidirectional GPIO port A pin 6 with SPI1 MISO, ADC channel 6, and timer channel 1 alternate functions.
32 PA7 bidirectional GPIO port A pin 7 with SPI1 MOSI, ADC channel 7, timer channel 2, and Ethernet MII/RMII receive alternate functions.
33 PC4 bidirectional GPIO port C pin 4 with ADC channel 14 and Ethernet MII/RMII receive data 0 alternate functions.
34 PC5 bidirectional GPIO port C pin 5 with ADC channel 15 and Ethernet MII/RMII receive data 1 alternate functions.
35 PB0 bidirectional GPIO port B pin 0 with ADC channel 8 and Ethernet MII receive data 2 alternate functions.
36 PB1 bidirectional GPIO port B pin 1 with ADC channel 9 and Ethernet MII receive data 3 alternate functions.
37 PB2 bidirectional GPIO port B pin 2 with 5V tolerance and BOOT1 configuration capability.
38 PE7 bidirectional GPIO port E pin 7 with 5V tolerance and timer 1 external trigger alternate function.
39 PE8 bidirectional GPIO port E pin 8 with 5V tolerance and timer 1 complementary channel 1 alternate function.
40 PE9 bidirectional GPIO port E pin 9 with 5V tolerance and timer 1 channel 1 alternate function.
41 PE10 bidirectional GPIO port E pin 10 with 5V tolerance and timer 1 complementary channel 2 alternate function.
42 PE11 bidirectional GPIO port E pin 11 with 5V tolerance and timer 1 channel 2 alternate function.
43 PE12 bidirectional GPIO port E pin 12 with 5V tolerance and timer 1 complementary channel 3 alternate function.
44 PE13 bidirectional GPIO port E pin 13 with 5V tolerance and timer 1 channel 3 alternate function.
45 PE14 bidirectional GPIO port E pin 14 with 5V tolerance and timer 1 channel 4 alternate function.
46 PE15 bidirectional GPIO port E pin 15 with 5V tolerance and timer 1 break-in alternate function.
47 PB10 bidirectional GPIO port B pin 10 with 5V tolerance, I2C2 clock, USART3 TX, and Ethernet MII RX error alternate functions.
48 PB11 bidirectional GPIO port B pin 11 with 5V tolerance, I2C2 data, USART3 RX, and Ethernet MII/RMII transmit enable alternate functions.
49 VSS_1 power_in Ground supply pin 1.
50 VDD_1 power_in Main digital power supply pin 1 (2.0 V to 3.6 V).
51 PB12 bidirectional GPIO port B pin 12 with 5V tolerance, SPI2 NSS, I2C2 SMBA, USART3 clock, CAN2 RX, and Ethernet MII/RMII transmit data 0 alternate functions.
52 PB13 bidirectional GPIO port B pin 13 with 5V tolerance, SPI2 clock, I2S2 clock, USART3 CTS, CAN2 TX, and Ethernet MII/RMII transmit data 1 alternate functions.
53 PB14 bidirectional GPIO port B pin 14 with 5V tolerance, SPI2 MISO, timer 1 complementary channel 2, and USART3 RTS alternate functions.
54 PB15 bidirectional GPIO port B pin 15 with 5V tolerance, SPI2 MOSI, I2S2 data, and timer 1 complementary channel 3 alternate functions.
55 PD8 bidirectional GPIO port D pin 8 with 5V tolerance, USART3 TX, and Ethernet MII/RMII receive alternate functions.
56 PD9 bidirectional GPIO port D pin 9 with 5V tolerance, USART3 RX, and Ethernet MII/RMII receive data 0 alternate functions.
57 PD10 bidirectional GPIO port D pin 10 with 5V tolerance, USART3 clock, and Ethernet MII/RMII receive data 1 alternate functions.
58 PD11 bidirectional GPIO port D pin 11 with 5V tolerance, USART3 CTS, and Ethernet MII receive data 2 alternate functions.
59 PD12 bidirectional GPIO port D pin 12 with 5V tolerance, timer 4 channel 1, USART3 RTS, and Ethernet MII receive data 3 alternate functions.
60 PD13 bidirectional GPIO port D pin 13 with 5V tolerance and timer 4 channel 2 alternate function.
61 PD14 bidirectional GPIO port D pin 14 with 5V tolerance and timer 4 channel 3 alternate function.
62 PD15 bidirectional GPIO port D pin 15 with 5V tolerance and timer 4 channel 4 alternate function.
63 PC6 bidirectional GPIO port C pin 6 with 5V tolerance, I2S2 master clock, and timer 3 channel 1 alternate functions.
64 PC7 bidirectional GPIO port C pin 7 with 5V tolerance, I2S3 master clock, and timer 3 channel 2 alternate functions.
65 PC8 bidirectional GPIO port C pin 8 with 5V tolerance and timer 3 channel 3 alternate function.
66 PC9 bidirectional GPIO port C pin 9 with 5V tolerance and timer 3 channel 4 alternate function.
67 PA8 bidirectional GPIO port A pin 8 with 5V tolerance, USART1 clock, USB OTG FS SOF, timer 1 channel 1, and MCO alternate functions.
68 PA9 bidirectional GPIO port A pin 9 with 5V tolerance, USART1 TX, timer 1 channel 2, and USB OTG FS VBUS alternate functions.
69 PA10 bidirectional GPIO port A pin 10 with 5V tolerance, USART1 RX, timer 1 channel 3, and USB OTG FS ID alternate functions.
70 PA11 bidirectional GPIO port A pin 11 with 5V tolerance, USART1 CTS, CAN1 RX, timer 1 channel 4, and USB OTG FS DM alternate functions.
71 PA12 bidirectional GPIO port A pin 12 with 5V tolerance, USART1 RTS, USB OTG FS DP, CAN1 TX, and timer 1 ETR alternate functions.
72 PA13 bidirectional JTAG test mode select (TMS) or Serial Wire debug data I/O (SWDIO) pin with 5V tolerance.
73 NC unconnected Not connected pin position in LQFP100 package.
74 VSS_2 power_in Ground supply pin 2.
75 VDD_2 power_in Main digital power supply pin 2 (2.0 V to 3.6 V).
76 PA14 bidirectional JTAG test clock (TCK) or Serial Wire debug clock (SWCLK) pin with 5V tolerance.
77 PA15 bidirectional JTAG data input (JTDI) pin with 5V tolerance, SPI3 NSS, I2S3 word select, timer, and alternate function remapping.
78 PC10 bidirectional GPIO port C pin 10 with 5V tolerance, UART4 TX, USART3 TX, SPI3 clock, and I2S3 clock alternate functions.
79 PC11 bidirectional GPIO port C pin 11 with 5V tolerance, UART4 RX, USART3 RX, and SPI3 MISO alternate functions.
80 PC12 bidirectional GPIO port C pin 12 with 5V tolerance, UART5 TX, USART3 clock, SPI3 MOSI, and I2S3 data alternate functions.
81 PD0 bidirectional GPIO port D pin 0 with 5V tolerance, main oscillator input, and CAN1 RX alternate functions.
82 PD1 bidirectional GPIO port D pin 1 with 5V tolerance, main oscillator output, and CAN1 TX alternate functions.
83 PD2 bidirectional GPIO port D pin 2 with 5V tolerance, timer 3 external trigger, and UART5 RX alternate functions.
84 PD3 bidirectional GPIO port D pin 3 with 5V tolerance and USART2 CTS alternate function.
85 PD4 bidirectional GPIO port D pin 4 with 5V tolerance and USART2 RTS alternate function.
86 PD5 bidirectional GPIO port D pin 5 with 5V tolerance and USART2 TX alternate function.
87 PD6 bidirectional GPIO port D pin 6 with 5V tolerance and USART2 RX alternate function.
88 PD7 bidirectional GPIO port D pin 7 with 5V tolerance and USART2 clock alternate function.
89 PB3 bidirectional JTAG data output (JTDO) pin with 5V tolerance, SPI3 clock, I2S3 clock, trace SWO, timer, and alternate functions.
90 PB4 bidirectional JTAG nTRST (test reset) pin with 5V tolerance, SPI3 MISO, timer 3 channel 1, and alternate functions.
91 PB5 bidirectional GPIO port B pin 5, I2C1 SMBus alert, SPI3 MOSI, Ethernet PPS output, and I2S3 data alternate functions.
92 PB6 bidirectional GPIO port B pin 6 with 5V tolerance, I2C1 clock, timer 4 channel 1, USART1 TX, and CAN2 TX alternate functions.
93 PB7 bidirectional GPIO port B pin 7 with 5V tolerance, I2C1 data, timer 4 channel 2, and USART1 RX alternate functions.
94 BOOT0 input Boot configuration input pin (0 = boot from main Flash, 1 = boot from system memory bootloader).
95 PB8 bidirectional GPIO port B pin 8 with 5V tolerance, timer 4 channel 3, Ethernet MII transmit data 3, I2C1 clock, and CAN1 RX alternate functions.
96 PB9 bidirectional GPIO port B pin 9 with 5V tolerance, timer 4 channel 4, I2C1 data, and CAN1 TX alternate functions.
97 PE0 bidirectional GPIO port E pin 0 with 5V tolerance and timer 4 external trigger alternate function.
98 PE1 bidirectional GPIO port E pin 1 with 5V tolerance.
99 VSS_3 power_in Ground supply pin 3.
100 VDD_3 power_in Main digital power supply pin 3 (2.0 V to 3.6 V).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F107VCT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f107vct6-etched.step / stm32f107vct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f107vct6.step / stm32f107vct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (104 pp, sha256 04f979ad6ea16a85, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF