component
STM32F107RBT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
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STM32F107RBT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32F107RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Power supply for the RTC, the 32 kHz oscillator and backup registers when VDD is not present, specified at 1.8 to 3.6 V. |
| 2 | PC13-TAMPER-RTC | bidirectional | General-purpose I/O (not 5 V tolerant) supplied through the power switch, so in output mode it is limited to 2 MHz with a maximum load of 30 pF and only one such pin may be an output at a time; alternate function TAMPER-RTC. |
| 3 | PC14-OSC32_IN | bidirectional | General-purpose I/O (not 5 V tolerant) on the backup supply with the same output limits (2 MHz, 30 pF, one pin at a time); alternate function OSC32_IN for the 32 kHz crystal. |
| 4 | PC15-OSC32_OUT | bidirectional | General-purpose I/O (not 5 V tolerant) on the backup supply with the same output limits (2 MHz, 30 pF, one pin at a time); alternate function OSC32_OUT for the 32 kHz crystal. |
| 5 | OSC_IN | input | External 3 to 25 MHz crystal oscillator input after reset; on LQFP64 the PD0 function can be remapped to this pin by software. |
| 6 | OSC_OUT | output | External 3 to 25 MHz crystal oscillator output after reset; on LQFP64 the PD1 function can be remapped to this pin by software. |
| 7 | NRST | bidirectional | Device reset pin, listed as I/O in the pin definition table; its electrical characteristics are in Section 5.3.14, which is not in the provided text. |
| 8 | PC0 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate function ADC12_IN10 analog input. |
| 9 | PC1 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN11 and Ethernet MDC (ETH_MII_MDC / ETH_RMII_MDC). |
| 10 | PC2 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN12 and ETH_MII_TXD2. |
| 11 | PC3 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN13 and ETH_MII_TX_CLK. |
| 12 | VSSA | power_in | Analog ground for the ADC, reset blocks, RCs and PLL, which must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply of 2.0 to 3.6 V for the ADC, reset blocks, RCs and PLL, which must be connected to VDD; minimum 2.4 V when the ADC is used. |
| 14 | PA0-WKUP | bidirectional | General-purpose I/O (not 5 V tolerant) with wakeup function WKUP and alternate functions ADC12_IN0, USART2_CTS, TIM2_CH1_ETR, TIM5_CH1 and ETH_MII_CRS_WKUP. |
| 15 | PA1 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions USART2_RTS, ADC12_IN1, TIM5_CH2, TIM2_CH2 and ETH_MII_RX_CLK / ETH_RMII_REF_CLK. |
| 16 | PA2 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions USART2_TX, TIM5_CH3, ADC12_IN2, TIM2_CH3 and ETH_MII_MDIO / ETH_RMII_MDIO. |
| 17 | PA3 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions USART2_RX, TIM5_CH4, ADC12_IN3, TIM2_CH4 and ETH_MII_COL. |
| 18 | VSS_4 | power_in | Ground for the digital I/O and core logic. |
| 19 | VDD_4 | power_in | Digital supply of 2.0 to 3.6 V for the I/Os and the internal regulator. |
| 20 | PA4 | bidirectional | 5 V tolerant I/O? No: standard (not 5 V tolerant) I/O with alternate functions SPI1_NSS, DAC_OUT1, USART2_CK and ADC12_IN4, and remap function SPI3_NSS / I2S3_WS. |
| 21 | PA5 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions SPI1_SCK, DAC_OUT2 and ADC12_IN5. |
| 22 | PA6 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions SPI1_MISO, ADC12_IN6, TIM3_CH1, and remap TIM1_BKIN. |
| 23 | PA7 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions SPI1_MOSI, ADC12_IN7, TIM3_CH2, ETH_MII_RX_DV / ETH_RMII_CRS_DV, and remap TIM1_CH1N. |
| 24 | PC4 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN14, ETH_MII_RXD0 and ETH_RMII_RXD0. |
| 25 | PC5 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN15, ETH_MII_RXD1 and ETH_RMII_RXD1. |
| 26 | PB0 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN8, TIM3_CH3, ETH_MII_RXD2, and remap TIM1_CH2N. |
| 27 | PB1 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN9, TIM3_CH4, ETH_MII_RXD3, and remap TIM1_CH3N. |
| 28 | PB2 | bidirectional | 5 V tolerant (FT) general-purpose I/O, also used as BOOT1 in the pin name; no alternate function is listed for this pin in the table. |
| 29 | PB10 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C2_SCL, USART3_TX, ETH_MII_RX_ER and remap TIM2_CH3; I2C2 is not available when Ethernet is in use. |
| 30 | PB11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C2_SDA, USART3_RX, ETH_MII_TX_EN / ETH_RMII_TX_EN and remap TIM2_CH4; I2C2 is not available when Ethernet is in use. |
| 31 | VSS_1 | power_in | Ground for the digital I/O and core logic. |
| 32 | VDD_1 | power_in | Digital supply of 2.0 to 3.6 V for the I/Os and the internal regulator. |
| 33 | PB12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_NSS / I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, ETH_MII_TXD0 and ETH_RMII_TXD0. |
| 34 | PB13 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_SCK / I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, ETH_MII_TXD1 and ETH_RMII_TXD1. |
| 35 | PB14 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_MISO, TIM1_CH2N and USART3_RTS. |
| 36 | PB15 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_MOSI / I2S2_SD and TIM1_CH3N. |
| 37 | PC6 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2S2_MCK and TIM3_CH1. |
| 38 | PC7 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2S3_MCK and TIM3_CH2. |
| 39 | PC8 | bidirectional | 5 V tolerant (FT) I/O with alternate function TIM3_CH3. |
| 40 | PC9 | bidirectional | 5 V tolerant (FT) I/O with alternate function TIM3_CH4. |
| 41 | PA8 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_CK, OTG_FS_SOF, TIM1_CH1 and MCO. |
| 42 | PA9 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_TX, TIM1_CH2 and OTG_FS_VBUS. |
| 43 | PA10 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_RX, TIM1_CH3 and OTG_FS_ID. |
| 44 | PA11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM. |
| 45 | PA12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_RTS, OTG_FS_DP, CAN1_TX and TIM1_ETR. |
| 46 | PA13 | bidirectional | 5 V tolerant (FT) I/O; default function JTMS-SWDIO (serial wire debug data). |
| 47 | VSS_2 | power_in | Ground for the digital I/O and core logic. |
| 48 | VDD_2 | power_in | Digital supply of 2.0 to 3.6 V for the I/Os and the internal regulator. |
| 49 | PA14 | bidirectional | 5 V tolerant (FT) I/O; default function JTCK-SWCLK (serial wire debug clock). |
| 50 | PA15 | bidirectional | 5 V tolerant (FT) I/O; default function JTDI, with alternate functions SPI3_NSS / I2S3_WS and TIM2_CH1_ETR, and remap SPI1_NSS. |
| 51 | PC10 | bidirectional | 5 V tolerant (FT) I/O with alternate functions UART4_TX, USART3_TX, SPI3_SCK and I2S3_CK. |
| 52 | PC11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions UART4_RX, USART3_RX and SPI3_MISO. |
| 53 | PC12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions UART5_TX, USART3_CK, SPI3_MOSI and I2S3_SD. |
| 54 | PD2 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM3_ETR and UART5_RX. |
| 55 | PB3 | bidirectional | 5 V tolerant (FT) I/O; default function JTDO, with alternate functions SPI3_SCK / I2S3_CK, TRACESWO, TIM2_CH2 and SPI1_SCK (remap). |
| 56 | PB4 | bidirectional | 5 V tolerant (FT) I/O; default function NJTRST, with alternate functions SPI3_MISO, TIM3_CH1 and SPI1_MISO (remap). |
| 57 | PB5 | bidirectional | Standard (not 5 V tolerant) I/O with alternate functions I2C1_SMBA, SPI3_MOSI, ETH_MII_PPS_OUT, I2S3_SD, TIM3_CH2, SPI1_MOSI and CAN2_RX. |
| 58 | PB6 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C1_SCL, TIM4_CH1, and remap USART1_TX and CAN2_TX. |
| 59 | PB7 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C1_SDA, TIM4_CH2, and remap USART1_RX. |
| 60 | BOOT0 | input | Boot-mode select pin sampled at startup to choose user Flash, system memory or embedded SRAM boot. |
| 61 | PB8 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM4_CH3, ETH_MII_TXD3, I2C1_SCL and CAN1_RX. |
| 62 | PB9 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM4_CH4, I2C1_SDA and CAN1_TX. |
| 63 | VSS_3 | power_in | Ground for the digital I/O and core logic. |
| 64 | VDD_3 | power_in | Digital supply of 2.0 to 3.6 V for the I/Os and the internal regulator. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32F107RBT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32f107rbt6-etched.step/stm32f107rbt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f107rbt6.step/stm32f107rbt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (104 pp, sha256
04f979ad6ea16a85, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STM32F107RBT6
**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32F107RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Power supply for the RTC, the 32 kHz oscillator and backup registers when VDD is not present, specified at 1.8 to 3.6 V. |
| 2 | PC13-TAMPER-RTC | bidirectional | General-purpose I/O (not 5 V tolerant) supplied through the power switch, so in output mode it is limited to 2 MHz with a maximum load of 30 pF and only one such pin may be an output at a time; alternate function TAMPER-RTC. |
| 3 | PC14-OSC32_IN | bidirectional | General-purpose I/O (not 5 V tolerant) on the backup supply with the same output limits (2 MHz, 30 pF, one pin at a time); alternate function OSC32_IN for the 32 kHz crystal. |
| 4 | PC15-OSC32_OUT | bidirectional | General-purpose I/O (not 5 V tolerant) on the backup supply with the same output limits (2 MHz, 30 pF, one pin at a time); alternate function OSC32_OUT for the 32 kHz crystal. |
| 5 | OSC_IN | input | External 3 to 25 MHz crystal oscillator input after reset; on LQFP64 the PD0 function can be remapped to this pin by software. |
| 6 | OSC_OUT | output | External 3 to 25 MHz crystal oscillator output after reset; on LQFP64 the PD1 function can be remapped to this pin by software. |
| 7 | NRST | bidirectional | Device reset pin, listed as I/O in the pin definition table; its electrical characteristics are in Section 5.3.14, which is not in the provided text. |
| 8 | PC0 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate function ADC12_IN10 analog input. |
| 9 | PC1 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN11 and Ethernet MDC (ETH_MII_MDC / ETH_RMII_MDC). |
| 10 | PC2 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN12 and ETH_MII_TXD2. |
| 11 | PC3 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN13 and ETH_MII_TX_CLK. |
| 12 | VSSA | power_in | Analog ground for the ADC, reset blocks, RCs and PLL, which must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply of 2.0 to 3.6 V for the ADC, reset blocks, RCs and PLL, which must be connected to VDD; minimum 2.4 V when the ADC is used. |
| 14 | PA0-WKUP | bidirectional | General-purpose I/O (not 5 V tolerant) with wakeup function WKUP and alternate functions ADC12_IN0, USART2_CTS, TIM2_CH1_ETR, TIM5_CH1 and ETH_MII_CRS_WKUP. |
| 15 | PA1 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions USART2_RTS, ADC12_IN1, TIM5_CH2, TIM2_CH2 and ETH_MII_RX_CLK / ETH_RMII_REF_CLK. |
| 16 | PA2 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions USART2_TX, TIM5_CH3, ADC12_IN2, TIM2_CH3 and ETH_MII_MDIO / ETH_RMII_MDIO. |
| 17 | PA3 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions USART2_RX, TIM5_CH4, ADC12_IN3, TIM2_CH4 and ETH_MII_COL. |
| 18 | VSS_4 | power_in | Ground for the digital I/O and core logic. |
| 19 | VDD_4 | power_in | Digital supply of 2.0 to 3.6 V for the I/Os and the internal regulator. |
| 20 | PA4 | bidirectional | 5 V tolerant I/O? No: standard (not 5 V tolerant) I/O with alternate functions SPI1_NSS, DAC_OUT1, USART2_CK and ADC12_IN4, and remap function SPI3_NSS / I2S3_WS. |
| 21 | PA5 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions SPI1_SCK, DAC_OUT2 and ADC12_IN5. |
| 22 | PA6 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions SPI1_MISO, ADC12_IN6, TIM3_CH1, and remap TIM1_BKIN. |
| 23 | PA7 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions SPI1_MOSI, ADC12_IN7, TIM3_CH2, ETH_MII_RX_DV / ETH_RMII_CRS_DV, and remap TIM1_CH1N. |
| 24 | PC4 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN14, ETH_MII_RXD0 and ETH_RMII_RXD0. |
| 25 | PC5 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN15, ETH_MII_RXD1 and ETH_RMII_RXD1. |
| 26 | PB0 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN8, TIM3_CH3, ETH_MII_RXD2, and remap TIM1_CH2N. |
| 27 | PB1 | bidirectional | General-purpose I/O (not 5 V tolerant) with alternate functions ADC12_IN9, TIM3_CH4, ETH_MII_RXD3, and remap TIM1_CH3N. |
| 28 | PB2 | bidirectional | 5 V tolerant (FT) general-purpose I/O, also used as BOOT1 in the pin name; no alternate function is listed for this pin in the table. |
| 29 | PB10 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C2_SCL, USART3_TX, ETH_MII_RX_ER and remap TIM2_CH3; I2C2 is not available when Ethernet is in use. |
| 30 | PB11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C2_SDA, USART3_RX, ETH_MII_TX_EN / ETH_RMII_TX_EN and remap TIM2_CH4; I2C2 is not available when Ethernet is in use. |
| 31 | VSS_1 | power_in | Ground for the digital I/O and core logic. |
| 32 | VDD_1 | power_in | Digital supply of 2.0 to 3.6 V for the I/Os and the internal regulator. |
| 33 | PB12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_NSS / I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, ETH_MII_TXD0 and ETH_RMII_TXD0. |
| 34 | PB13 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_SCK / I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, ETH_MII_TXD1 and ETH_RMII_TXD1. |
| 35 | PB14 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_MISO, TIM1_CH2N and USART3_RTS. |
| 36 | PB15 | bidirectional | 5 V tolerant (FT) I/O with alternate functions SPI2_MOSI / I2S2_SD and TIM1_CH3N. |
| 37 | PC6 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2S2_MCK and TIM3_CH1. |
| 38 | PC7 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2S3_MCK and TIM3_CH2. |
| 39 | PC8 | bidirectional | 5 V tolerant (FT) I/O with alternate function TIM3_CH3. |
| 40 | PC9 | bidirectional | 5 V tolerant (FT) I/O with alternate function TIM3_CH4. |
| 41 | PA8 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_CK, OTG_FS_SOF, TIM1_CH1 and MCO. |
| 42 | PA9 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_TX, TIM1_CH2 and OTG_FS_VBUS. |
| 43 | PA10 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_RX, TIM1_CH3 and OTG_FS_ID. |
| 44 | PA11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM. |
| 45 | PA12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions USART1_RTS, OTG_FS_DP, CAN1_TX and TIM1_ETR. |
| 46 | PA13 | bidirectional | 5 V tolerant (FT) I/O; default function JTMS-SWDIO (serial wire debug data). |
| 47 | VSS_2 | power_in | Ground for the digital I/O and core logic. |
| 48 | VDD_2 | power_in | Digital supply of 2.0 to 3.6 V for the I/Os and the internal regulator. |
| 49 | PA14 | bidirectional | 5 V tolerant (FT) I/O; default function JTCK-SWCLK (serial wire debug clock). |
| 50 | PA15 | bidirectional | 5 V tolerant (FT) I/O; default function JTDI, with alternate functions SPI3_NSS / I2S3_WS and TIM2_CH1_ETR, and remap SPI1_NSS. |
| 51 | PC10 | bidirectional | 5 V tolerant (FT) I/O with alternate functions UART4_TX, USART3_TX, SPI3_SCK and I2S3_CK. |
| 52 | PC11 | bidirectional | 5 V tolerant (FT) I/O with alternate functions UART4_RX, USART3_RX and SPI3_MISO. |
| 53 | PC12 | bidirectional | 5 V tolerant (FT) I/O with alternate functions UART5_TX, USART3_CK, SPI3_MOSI and I2S3_SD. |
| 54 | PD2 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM3_ETR and UART5_RX. |
| 55 | PB3 | bidirectional | 5 V tolerant (FT) I/O; default function JTDO, with alternate functions SPI3_SCK / I2S3_CK, TRACESWO, TIM2_CH2 and SPI1_SCK (remap). |
| 56 | PB4 | bidirectional | 5 V tolerant (FT) I/O; default function NJTRST, with alternate functions SPI3_MISO, TIM3_CH1 and SPI1_MISO (remap). |
| 57 | PB5 | bidirectional | Standard (not 5 V tolerant) I/O with alternate functions I2C1_SMBA, SPI3_MOSI, ETH_MII_PPS_OUT, I2S3_SD, TIM3_CH2, SPI1_MOSI and CAN2_RX. |
| 58 | PB6 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C1_SCL, TIM4_CH1, and remap USART1_TX and CAN2_TX. |
| 59 | PB7 | bidirectional | 5 V tolerant (FT) I/O with alternate functions I2C1_SDA, TIM4_CH2, and remap USART1_RX. |
| 60 | BOOT0 | input | Boot-mode select pin sampled at startup to choose user Flash, system memory or embedded SRAM boot. |
| 61 | PB8 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM4_CH3, ETH_MII_TXD3, I2C1_SCL and CAN1_RX. |
| 62 | PB9 | bidirectional | 5 V tolerant (FT) I/O with alternate functions TIM4_CH4, I2C1_SDA and CAN1_TX. |
| 63 | VSS_3 | power_in | Ground for the digital I/O and core logic. |
| 64 | VDD_3 | power_in | Digital supply of 2.0 to 3.6 V for the I/Os and the internal regulator. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
## CAD (KiCad official)
- Symbol: `STM32F107RBT6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `stm32f107rbt6-etched.step` / `stm32f107rbt6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32f107rbt6.step` / `stm32f107rbt6.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586182164152639488) (104 pp, sha256 `04f979ad6ea16a85`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stm32f107rbt6-datasheet.pdf)