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STM32F105VBT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f105vbt6factory-2.0.0extractor-text
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STM32F105VBT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F105VBT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant GPIO PE2; alternate function TRACECK (ETM trace clock).
2 PE3 bidirectional 5 V-tolerant GPIO PE3; alternate function TRACED0 (ETM trace).
3 PE4 bidirectional 5 V-tolerant GPIO PE4; alternate function TRACED1 (ETM trace).
4 PE5 bidirectional 5 V-tolerant GPIO PE5; alternate function TRACED2 (ETM trace).
5 PE6 bidirectional 5 V-tolerant GPIO PE6; alternate function TRACED3 (ETM trace).
6 VBAT power_in Power supply for the RTC, the 32 kHz oscillator and backup registers when VDD is not present, 1.8 to 3.6 V.
7 PC13-TAMPER-RTC bidirectional GPIO PC13 supplied through the power switch, usable in output only at 2 MHz with max 30 pF load and only one such pin at a time; alternate function TAMPER-RTC.
8 PC14-OSC32_IN bidirectional GPIO PC14 supplied through the power switch, usable in output only at 2 MHz with max 30 pF load and only one such pin at a time; alternate function OSC32_IN (32 kHz oscillator input).
9 PC15-OSC32_OUT bidirectional GPIO PC15 supplied through the power switch, usable in output only at 2 MHz with max 30 pF load and only one such pin at a time; alternate function OSC32_OUT (32 kHz oscillator output).
10 VSS_5 power_in Digital ground pin.
11 VDD_5 power_in Digital supply for I/Os and internal regulator, 2.0 to 3.6 V.
12 OSC_IN input HSE oscillator input for a 3-25 MHz crystal or external clock.
13 OSC_OUT output HSE oscillator output for a 3-25 MHz crystal.
14 NRST bidirectional Active-low reset pin; electrical limits are given in Section 5.3.14 (NRST pin characteristics).
15 PC0 bidirectional Standard GPIO PC0 (not 5 V tolerant per Table 5); alternate function ADC12_IN10 analog input.
16 PC1 bidirectional Standard GPIO PC1 (not 5 V tolerant per Table 5); alternate functions ADC12_IN11 and Ethernet MDC.
17 PC2 bidirectional Standard GPIO PC2 (not 5 V tolerant per Table 5); alternate functions ADC12_IN12 and ETH_MII_TXD2.
18 PC3 bidirectional Standard GPIO PC3 (not 5 V tolerant per Table 5); alternate functions ADC12_IN13 and ETH_MII_TX_CLK.
19 VSSA power_in Analog ground for the ADC, reset blocks, RCs and PLL; must be connected to VSS.
20 VREF- power_in Negative reference voltage input for the ADC.
21 VREF+ power_in Positive reference voltage input for the ADC and DAC.
22 VDDA power_in Analog supply for the ADC, reset blocks, RCs and PLL, 2.0 to 3.6 V; minimum 2.4 V when the ADC is used; must be connected to VDD.
23 PA0-WKUP bidirectional Standard GPIO PA0; WKUP wakeup input, with alternate functions ADC12_IN0, TIM2_CH1_ETR, USART2_CTS and TIM5_CH1.
24 PA1 bidirectional Standard GPIO PA1; alternate functions USART2_RTS, ADC12_IN1, TIM5_CH2 and TIM2_CH2.
25 PA2 bidirectional Standard GPIO PA2; alternate functions USART2_TX, TIM5_CH3, ADC12_IN2 and TIM2_CH3.
26 PA3 bidirectional Standard GPIO PA3; alternate functions USART2_RX, TIM5_CH4, ADC12_IN3 and TIM2_CH4.
27 VSS_4 power_in Digital ground pin.
28 VDD_4 power_in Digital supply for I/Os and internal regulator, 2.0 to 3.6 V.
29 PA4 bidirectional Standard GPIO PA4; alternate functions DAC_OUT1, ADC12_IN4, SPI1_NSS, USART2_CK and SPI3_NSS/I2S3_WS.
30 PA5 bidirectional Standard GPIO PA5; alternate functions DAC_OUT2, ADC12_IN5 and SPI1_SCK.
31 PA6 bidirectional Standard GPIO PA6; alternate functions SPI1_MISO, ADC12_IN6, TIM3_CH1 and TIM1_BKIN.
32 PA7 bidirectional Standard GPIO PA7; alternate functions SPI1_MOSI, ADC12_IN7, TIM3_CH2, TIM1_CH1N and Ethernet RX_DV/CRS_DV.
33 PC4 bidirectional Standard GPIO PC4; alternate functions ADC12_IN14 and Ethernet RXD0.
34 PC5 bidirectional Standard GPIO PC5; alternate functions ADC12_IN15 and Ethernet RXD1.
35 PB0 bidirectional Standard GPIO PB0; alternate functions ADC12_IN8, TIM3_CH3, TIM1_CH2N and Ethernet RXD2.
36 PB1 bidirectional Standard GPIO PB1; alternate functions ADC12_IN9, TIM3_CH4, TIM1_CH3N and Ethernet RXD3.
37 PB2/BOOT1 bidirectional 5 V-tolerant GPIO PB2 that shares its pin with the BOOT1 boot-mode selection function.
38 PE7 bidirectional 5 V-tolerant GPIO PE7; alternate function TIM1_ETR.
39 PE8 bidirectional 5 V-tolerant GPIO PE8; alternate function TIM1_CH1N.
40 PE9 bidirectional 5 V-tolerant GPIO PE9; alternate function TIM1_CH1.
41 PE10 bidirectional 5 V-tolerant GPIO PE10; alternate function TIM1_CH2N.
42 PE11 bidirectional 5 V-tolerant GPIO PE11; alternate function TIM1_CH2.
43 PE12 bidirectional 5 V-tolerant GPIO PE12; alternate function TIM1_CH3N.
44 PE13 bidirectional 5 V-tolerant GPIO PE13; alternate function TIM1_CH3.
45 PE14 bidirectional 5 V-tolerant GPIO PE14; alternate function TIM1_CH4.
46 PE15 bidirectional 5 V-tolerant GPIO PE15; alternate function TIM1_BKIN.
47 PB10 bidirectional 5 V-tolerant GPIO PB10; alternate functions I2C2_SCL, USART3_TX, Ethernet RX_ER and TIM2_CH3 (I2C2 not available when Ethernet is used).
48 PB11 bidirectional 5 V-tolerant GPIO PB11; alternate functions I2C2_SDA, USART3_RX, Ethernet TX_EN and TIM2_CH4 (I2C2 not available when Ethernet is used).
49 VSS_1 power_in Digital ground pin.
50 VDD_1 power_in Digital supply for I/Os and internal regulator, 2.0 to 3.6 V.
51 PB12 bidirectional 5 V-tolerant GPIO PB12; alternate functions SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX and Ethernet TXD0.
52 PB13 bidirectional 5 V-tolerant GPIO PB13; alternate functions SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and Ethernet TXD1.
53 PB14 bidirectional 5 V-tolerant GPIO PB14; alternate functions SPI2_MISO, TIM1_CH2N and USART3_RTS.
54 PB15 bidirectional 5 V-tolerant GPIO PB15; alternate functions SPI2_MOSI/I2S2_SD and TIM1_CH3N.
55 PD8 bidirectional 5 V-tolerant GPIO PD8; alternate functions USART3_TX and Ethernet RX_DV/CRS_DV.
56 PD9 bidirectional 5 V-tolerant GPIO PD9; alternate functions USART3_RX and Ethernet RXD0.
57 PD10 bidirectional 5 V-tolerant GPIO PD10; alternate functions USART3_CK and Ethernet RXD1.
58 PD11 bidirectional 5 V-tolerant GPIO PD11; alternate functions USART3_CTS and Ethernet RXD2.
59 PD12 bidirectional 5 V-tolerant GPIO PD12; alternate functions TIM4_CH1, USART3_RTS and Ethernet RXD3.
60 PD13 bidirectional 5 V-tolerant GPIO PD13; alternate function TIM4_CH2.
61 PD14 bidirectional 5 V-tolerant GPIO PD14; alternate function TIM4_CH3.
62 PD15 bidirectional 5 V-tolerant GPIO PD15; alternate function TIM4_CH4.
63 PC6 bidirectional 5 V-tolerant GPIO PC6; alternate functions I2S2_MCK and TIM3_CH1.
64 PC7 bidirectional 5 V-tolerant GPIO PC7; alternate functions I2S3_MCK and TIM3_CH2.
65 PC8 bidirectional 5 V-tolerant GPIO PC8; alternate function TIM3_CH3.
66 PC9 bidirectional 5 V-tolerant GPIO PC9; alternate function TIM3_CH4.
67 PA8 bidirectional 5 V-tolerant GPIO PA8; alternate functions USART1_CK, OTG_FS_SOF, TIM1_CH1 and MCO.
68 PA9 bidirectional 5 V-tolerant GPIO PA9; alternate functions USART1_TX, TIM1_CH2 and OTG_FS_VBUS.
69 PA10 bidirectional 5 V-tolerant GPIO PA10; alternate functions USART1_RX, TIM1_CH3 and OTG_FS_ID.
70 PA11 bidirectional 5 V-tolerant GPIO PA11; alternate functions USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM.
71 PA12 bidirectional 5 V-tolerant GPIO PA12; alternate functions USART1_RTS, OTG_FS_DP, CAN1_TX and TIM1_ETR.
72 PA13 bidirectional 5 V-tolerant GPIO PA13; default function JTMS-SWDIO (serial wire debug data).
73 NC unconnected Pin marked 'Not connected' in Table 5 for the LQFP100 package; leave unconnected.
74 VSS_2 power_in Digital ground pin.
75 VDD_2 power_in Digital supply for I/Os and internal regulator, 2.0 to 3.6 V.
76 PA14 bidirectional 5 V-tolerant GPIO PA14; default function JTCK-SWCLK (serial wire debug clock).
77 PA15 bidirectional 5 V-tolerant GPIO PA15; default function JTDI; alternate functions SPI3_NSS/I2S3_WS, TIM2_CH1_ETR and SPI1_NSS.
78 PC10 bidirectional 5 V-tolerant GPIO PC10; alternate functions UART4_TX, USART3_TX and SPI3_SCK/I2S3_CK.
79 PC11 bidirectional 5 V-tolerant GPIO PC11; alternate functions UART4_RX, USART3_RX and SPI3_MISO.
80 PC12 bidirectional 5 V-tolerant GPIO PC12; alternate functions UART5_TX, USART3_CK and SPI3_MOSI/I2S3_SD.
81 PD0 bidirectional 5 V-tolerant GPIO PD0 available by default on LQFP100; alternate functions OSC_IN and CAN1_RX.
82 PD1 bidirectional 5 V-tolerant GPIO PD1 available by default on LQFP100; alternate functions OSC_OUT and CAN1_TX.
83 PD2 bidirectional 5 V-tolerant GPIO PD2; alternate functions TIM3_ETR and UART5_RX.
84 PD3 bidirectional 5 V-tolerant GPIO PD3; alternate function USART2_CTS.
85 PD4 bidirectional 5 V-tolerant GPIO PD4; alternate function USART2_RTS.
86 PD5 bidirectional 5 V-tolerant GPIO PD5; alternate function USART2_TX.
87 PD6 bidirectional 5 V-tolerant GPIO PD6; alternate function USART2_RX.
88 PD7 bidirectional 5 V-tolerant GPIO PD7; alternate function USART2_CK.
89 PB3 bidirectional 5 V-tolerant GPIO PB3; default function JTDO; alternate functions TRACESWO, TIM2_CH2, SPI3_SCK/I2S3_CK and SPI1_SCK.
90 PB4 bidirectional 5 V-tolerant GPIO PB4; default function NJTRST; alternate functions SPI3_MISO, TIM3_CH1 and SPI1_MISO.
91 PB5 bidirectional Standard GPIO PB5 (not 5 V tolerant per Table 5); alternate functions I2C1_SMBA, SPI3_MOSI/I2S3_SD, Ethernet PPS_OUT, TIM3_CH2, SPI1_MOSI and CAN2_RX.
92 PB6 bidirectional 5 V-tolerant GPIO PB6; alternate functions I2C1_SCL, TIM4_CH1, USART1_TX and CAN2_TX.
93 PB7 bidirectional 5 V-tolerant GPIO PB7; alternate functions I2C1_SDA, TIM4_CH2 and USART1_RX.
94 BOOT0 input Boot mode selection pin sampled at startup to select user Flash, system memory or embedded SRAM boot.
95 PB8 bidirectional 5 V-tolerant GPIO PB8; alternate functions TIM4_CH3, Ethernet TXD3, I2C1_SCL and CAN1_RX.
96 PB9 bidirectional 5 V-tolerant GPIO PB9; alternate functions TIM4_CH4, I2C1_SDA and CAN1_TX.
97 PE0 bidirectional 5 V-tolerant GPIO PE0; alternate function TIM4_ETR.
98 PE1 bidirectional 5 V-tolerant GPIO PE1; no alternate function listed in Table 5.
99 VSS_3 power_in Digital ground pin.
100 VDD_3 power_in Digital supply for I/Os and internal regulator, 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F105VBT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f105vbt6-etched.step / stm32f105vbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f105vbt6.step / stm32f105vbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (108 pp, sha256 ca4bad652e5eb36d, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF