component
STM32F105VBH6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LFBGA-100. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F105VBH6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LFBGA-100
STM32F105VBH6 from STMicroelectronics, in a LFBGA-100. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| A3 | PE2 | bidirectional | GPIO, 5 V tolerant (FT); default function PE2, alternate function TRACECK. |
| B3 | PE3 | bidirectional | GPIO, 5 V tolerant (FT); default function PE3, alternate function TRACED0. |
| C3 | PE4 | bidirectional | GPIO, 5 V tolerant (FT); default function PE4, alternate function TRACED1. |
| D3 | PE5 | bidirectional | GPIO, 5 V tolerant (FT); default function PE5, alternate function TRACED2. |
| E3 | PE6 | bidirectional | GPIO, 5 V tolerant (FT); default function PE6, alternate function TRACED3. |
| B2 | VBAT | power_in | Backup supply 1.8 to 3.6 V for the RTC, the 32 kHz oscillator and backup registers when VDD is not present. |
| A2 | PC13-TAMPER-RTC | bidirectional | GPIO PC13 (not 5 V tolerant) also used as TAMPER-RTC; supplied through the power switch, so output use is limited to 2 MHz mode with max 30 pF load and only one pin in output mode at a time. |
| A1 | PC14-OSC32_IN | bidirectional | GPIO PC14 (not 5 V tolerant) or OSC32_IN; supplied through the power switch, so output use is limited to 2 MHz mode with max 30 pF load and only one pin in output mode at a time. |
| B1 | PC15-OSC32_OUT | bidirectional | GPIO PC15 (not 5 V tolerant) or OSC32_OUT; supplied through the power switch, so output use is limited to 2 MHz mode with max 30 pF load and only one pin in output mode at a time. |
| C2 | VSS_5 | power_in | Digital ground. |
| D2 | VDD_5 | power_in | Digital supply 2.0 to 3.6 V for the I/Os and the internal regulator. |
| C1 | OSC_IN | input | External 3-25 MHz crystal oscillator input. |
| D1 | OSC_OUT | output | External 3-25 MHz crystal oscillator output. |
| E1 | NRST | bidirectional | Reset pin (I/O in Table 5); its electrical limits are in section 5.3.14, which is not in this excerpt. |
| F1 | PC0 | bidirectional | GPIO, not 5 V tolerant; alternate function ADC12_IN10. |
| F2 | PC1 | bidirectional | GPIO, not 5 V tolerant; alternate functions ADC12_IN11, ETH_MII_MDC and ETH_RMII_MDC. |
| E2 | PC2 | bidirectional | GPIO, not 5 V tolerant; alternate functions ADC12_IN12 and ETH_MII_TXD2. |
| F3 | PC3 | bidirectional | GPIO, not 5 V tolerant; alternate functions ADC12_IN13 and ETH_MII_TX_CLK. |
| G1 | VSSA | power_in | Analog ground, connected to VSS. |
| H1 | VREF- | power_in | Negative reference voltage pin for the ADC/DAC as listed in Table 5; no voltage limit is given in this excerpt. |
| J1 | VREF+ | power_in | Positive reference voltage input for the ADC/DAC; it may be tied to VDDA or kept separate per decoupling schemes in Figures 36 and 37. |
| K1 | VDDA | power_in | Analog supply 2.0 to 3.6 V for the ADC, reset blocks, RCs and PLL; minimum 2.4 V when the ADC is used; must be connected to VDD. |
| G2 | PA0-WKUP | bidirectional | GPIO, not 5 V tolerant; WKUP wakeup input, alternate functions include USART2_CTS, ADC12_IN0, TIM2_CH1_ETR, TIM5_CH1 and ETH_MII_CRS_WKUP. |
| H2 | PA1 | bidirectional | GPIO, not 5 V tolerant; alternate functions include USART2_RTS, ADC12_IN1, TIM5_CH2, TIM2_CH2 and ETH_MII_RX_CLK/ETH_RMII_REF_CLK. |
| J2 | PA2 | bidirectional | GPIO, not 5 V tolerant; alternate functions include USART2_TX, TIM5_CH3, ADC12_IN2, TIM2_CH3 and ETH_MII_MDIO/ETH_RMII_MDIO. |
| K2 | PA3 | bidirectional | GPIO, not 5 V tolerant; alternate functions include USART2_RX, TIM5_CH4, ADC12_IN3, TIM2_CH4 and ETH_MII_COL. |
| E4 | VSS_4 | power_in | Digital ground. |
| F4 | VDD_4 | power_in | Digital supply 2.0 to 3.6 V for the I/Os and the internal regulator. |
| G3 | PA4 | bidirectional | GPIO, not 5 V tolerant; alternate functions include SPI1_NSS, DAC_OUT1, USART2_CK, ADC12_IN4 and SPI3_NSS/I2S3_WS. |
| H3 | PA5 | bidirectional | GPIO, not 5 V tolerant; alternate functions include SPI1_SCK, DAC_OUT2 and ADC12_IN5. |
| J3 | PA6 | bidirectional | GPIO, not 5 V tolerant; alternate functions include SPI1_MISO, ADC12_IN6, TIM3_CH1 and TIM1_BKIN. |
| K3 | PA7 | bidirectional | GPIO, not 5 V tolerant; alternate functions include SPI1_MOSI, ADC12_IN7, TIM3_CH2, ETH_MII_RX_DV/ETH_RMII_CRS_DV and TIM1_CH1N. |
| G4 | PC4 | bidirectional | GPIO, not 5 V tolerant; alternate functions include ADC12_IN14 and ETH_MII_RXD0/ETH_RMII_RXD0. |
| H4 | PC5 | bidirectional | GPIO, not 5 V tolerant; alternate functions include ADC12_IN15 and ETH_MII_RXD1/ETH_RMII_RXD1. |
| J4 | PB0 | bidirectional | GPIO, not 5 V tolerant; alternate functions include ADC12_IN8, TIM3_CH3, ETH_MII_RXD2 and TIM1_CH2N. |
| K4 | PB1 | bidirectional | GPIO, not 5 V tolerant; alternate functions include ADC12_IN9, TIM3_CH4, ETH_MII_RXD3 and TIM1_CH3N. |
| G5 | PB2/BOOT1 | bidirectional | GPIO, 5 V tolerant (FT); main function PB2 with BOOT1 function. |
| H5 | PE7 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM1_ETR. |
| J5 | PE8 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM1_CH1N. |
| K5 | PE9 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM1_CH1. |
| G6 | PE10 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM1_CH2N. |
| H6 | PE11 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM1_CH2. |
| J6 | PE12 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM1_CH3N. |
| K6 | PE13 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM1_CH3. |
| G7 | PE14 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM1_CH4. |
| H7 | PE15 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM1_BKIN. |
| J7 | PB10 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include I2C2_SCL, USART3_TX, ETH_MII_RX_ER and TIM2_CH3; SPI2/I2S2 and I2C2 are not available when Ethernet is used. |
| K7 | PB11 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include I2C2_SDA, USART3_RX, ETH_MII_TX_EN/ETH_RMII_TX_EN and TIM2_CH4. |
| E7 | VSS_1 | power_in | Digital ground. |
| F7 | VDD_1 | power_in | Digital supply 2.0 to 3.6 V for the I/Os and the internal regulator. |
| K8 | PB12 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX and ETH_MII_TXD0/ETH_RMII_TXD0. |
| J8 | PB13 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and ETH_MII_TXD1/ETH_RMII_TXD1. |
| H8 | PB14 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include SPI2_MISO, TIM1_CH2N and USART3_RTS. |
| G8 | PB15 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include SPI2_MOSI, I2S2_SD and TIM1_CH3N. |
| K9 | PD8 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include USART3_TX and ETH_MII_RX_DV/ETH_RMII_CRS_DV. |
| J9 | PD9 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include USART3_RX, ETH_MII_RXD0 and ETH_RMII_RXD0. |
| H9 | PD10 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include USART3_CK, ETH_MII_RXD1 and ETH_RMII_RXD1. |
| G9 | PD11 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include USART3_CTS and ETH_MII_RXD2. |
| K10 | PD12 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include TIM4_CH1, USART3_RTS and ETH_MII_RXD3. |
| J10 | PD13 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM4_CH2. |
| H10 | PD14 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM4_CH3. |
| G10 | PD15 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM4_CH4. |
| F10 | PC6 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions I2S2_MCK and TIM3_CH1. |
| E10 | PC7 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions I2S3_MCK and TIM3_CH2. |
| F9 | PC8 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM3_CH3. |
| E9 | PC9 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM3_CH4. |
| D9 | PA8 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include USART1_CK, OTG_FS_SOF, TIM1_CH1 and MCO. |
| C9 | PA9 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include USART1_TX, TIM1_CH2 and OTG_FS_VBUS. |
| D10 | PA10 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include USART1_RX, TIM1_CH3 and OTG_FS_ID. |
| C10 | PA11 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM. |
| B10 | PA12 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include USART1_RTS, OTG_FS_DP, CAN1_TX and TIM1_ETR. |
| A10 | PA13 | bidirectional | GPIO, 5 V tolerant (FT); main function JTMS-SWDIO after reset. |
| F8 | NC | unconnected | Not connected. |
| E6 | VSS_2 | power_in | Digital ground. |
| F6 | VDD_2 | power_in | Digital supply 2.0 to 3.6 V for the I/Os and the internal regulator. |
| A9 | PA14 | bidirectional | GPIO, 5 V tolerant (FT); main function JTCK-SWCLK after reset. |
| A8 | PA15 | bidirectional | GPIO, 5 V tolerant (FT); main function JTDI after reset; alternate functions include SPI3_NSS/I2S3_WS, TIM2_CH1_ETR and SPI1_NSS. |
| B9 | PC10 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include UART4_TX, USART3_TX and SPI3_SCK/I2S3_CK. |
| B8 | PC11 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include UART4_RX, USART3_RX and SPI3_MISO. |
| C8 | PC12 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include UART5_TX, USART3_CK and SPI3_MOSI/I2S3_SD. |
| D8 | PD0 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions OSC_IN and CAN1_RX; on BGA100 PD0 is available by default without remapping. |
| E8 | PD1 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions OSC_OUT and CAN1_TX; on BGA100 PD1 is available by default without remapping. |
| B7 | PD2 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions TIM3_ETR and UART5_RX. |
| C7 | PD3 | bidirectional | GPIO, 5 V tolerant (FT); alternate function USART2_CTS. |
| D7 | PD4 | bidirectional | GPIO, 5 V tolerant (FT); alternate function USART2_RTS. |
| B6 | PD5 | bidirectional | GPIO, 5 V tolerant (FT); alternate function USART2_TX. |
| C6 | PD6 | bidirectional | GPIO, 5 V tolerant (FT); alternate function USART2_RX. |
| D6 | PD7 | bidirectional | GPIO, 5 V tolerant (FT); alternate function USART2_CK. |
| A7 | PB3 | bidirectional | GPIO, 5 V tolerant (FT); main function JTDO after reset; alternate functions include SPI3_SCK/I2S3_CK, TRACESWO, TIM2_CH2 and SPI1_SCK. |
| A6 | PB4 | bidirectional | GPIO, 5 V tolerant (FT); main function NJTRST after reset; alternate functions include SPI3_MISO, TIM3_CH1 and SPI1_MISO. |
| C5 | PB5 | bidirectional | GPIO, not 5 V tolerant; alternate functions include I2C1_SMBA, SPI3_MOSI, ETH_MII_PPS_OUT, I2S3_SD, TIM3_CH2, SPI1_MOSI and CAN2_RX. |
| B5 | PB6 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include I2C1_SCL, TIM4_CH1, USART1_TX and CAN2_TX. |
| A5 | PB7 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include I2C1_SDA, TIM4_CH2 and USART1_RX. |
| D5 | BOOT0 | input | Boot selection pin sampled at startup to choose User Flash, System Memory or embedded SRAM boot. |
| B4 | PB8 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include TIM4_CH3, ETH_MII_TXD3, I2C1_SCL and CAN1_RX. |
| A4 | PB9 | bidirectional | GPIO, 5 V tolerant (FT); alternate functions include TIM4_CH4, I2C1_SDA and CAN1_TX. |
| D4 | PE0 | bidirectional | GPIO, 5 V tolerant (FT); alternate function TIM4_ETR. |
| C4 | PE1 | bidirectional | GPIO, 5 V tolerant (FT); no alternate function listed in Table 5. |
| E5 | VSS_3 | power_in | Digital ground. |
| F5 | VDD_3 | power_in | Digital supply 2.0 to 3.6 V for the I/Os and the internal regulator. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LFBGA-100 |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
STM32F105VBH6 - Footprint:
Package_BGA:LFBGA-100_10x10mm_Layout10x10_P0.8mm - 3D model: LFBGA-100 (KiCad packages3D, STEP)
- 3D model files:
stm32f105vbh6-etched.step/stm32f105vbh6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f105vbh6.step/stm32f105vbh6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (108 pp, sha256
ca4bad652e5eb36d, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).