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STM32F103ZGT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f103zgt6factory-2.0.0extractor-text
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Symbol & Footprint

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Datasheet

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Contents

README

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STM32F103ZGT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

STM32F103ZGT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 output GPIO Port E pin 2, alternate functions TRACECK or FSMC_A23 address line.
2 PE3 output GPIO Port E pin 3, alternate functions TRACED0 or FSMC_A19 address line.
3 PE4 output GPIO Port E pin 4, alternate functions TRACED1 or FSMC_A20 address line.
4 PE5 bidirectional GPIO Port E pin 5, alternate functions TRACED2/FSMC_A21 or TIM9_CH1 capture/compare.
5 PE6 bidirectional GPIO Port E pin 6, alternate functions TRACED3/FSMC_A22 or TIM9_CH2 capture/compare.
6 VBAT power_in Power supply for RTC, backup registers, and external 32 kHz oscillator during low-power modes, 1.8 to 3.6 V.
7 PC13-TAMPER-RTC bidirectional GPIO Port C pin 13 with TAMPER-RTC function supplied through power switch with 3 mA limit, max speed 2 MHz at 30 pF load.
8 PC14-OSC32_IN bidirectional GPIO Port C pin 14 or low-speed external 32.768 kHz oscillator input, supplied through power switch.
9 PC15-OSC32_OUT bidirectional GPIO Port C pin 15 or low-speed external 32.768 kHz oscillator output, supplied through power switch.
10 PF0 bidirectional GPIO Port F pin 0, alternate function FSMC_A0 address line (5 V tolerant).
11 PF1 bidirectional GPIO Port F pin 1, alternate function FSMC_A1 address line (5 V tolerant).
12 PF2 bidirectional GPIO Port F pin 2, alternate function FSMC_A2 address line (5 V tolerant).
13 PF3 bidirectional GPIO Port F pin 3, alternate function FSMC_A3 address line (5 V tolerant).
14 PF4 bidirectional GPIO Port F pin 4, alternate function FSMC_A4 address line (5 V tolerant).
15 PF5 bidirectional GPIO Port F pin 5, alternate function FSMC_A5 address line (5 V tolerant).
16 VSS_5 power_in Ground reference for analog and digital circuits.
17 VDD_5 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
18 PF6 bidirectional GPIO Port F pin 6, alternate functions ADC3_IN4 analog input, FSMC_NIORD control signal, or TIM10_CH1 capture/compare.
19 PF7 bidirectional GPIO Port F pin 7, alternate functions ADC3_IN5 analog input, FSMC_NREG control signal, or TIM11_CH1 capture/compare.
20 PF8 bidirectional GPIO Port F pin 8, alternate functions ADC3_IN6 analog input, FSMC_NIOWR control signal, or TIM13_CH1 capture/compare.
21 PF9 bidirectional GPIO Port F pin 9, alternate functions ADC3_IN7 analog input, FSMC_CD control signal, or TIM14_CH1 capture/compare.
22 PF10 bidirectional GPIO Port F pin 10, alternate functions ADC3_IN8 analog input or FSMC_INTR interrupt signal.
23 OSC_IN input High-speed external oscillator input for 4 to 16 MHz crystal or clock source.
24 OSC_OUT output High-speed external oscillator output connection for 4 to 16 MHz crystal.
25 NRST bidirectional External active-low reset input with integrated pull-up resistor and Schmitt trigger, 100 ns filter.
26 PC0 bidirectional GPIO Port C pin 0, alternate function ADC123_IN10 analog input.
27 PC1 bidirectional GPIO Port C pin 1, alternate function ADC123_IN11 analog input.
28 PC2 bidirectional GPIO Port C pin 2, alternate function ADC123_IN12 analog input.
29 PC3 bidirectional GPIO Port C pin 3, alternate function ADC123_IN13 analog input.
30 VSSA power_in Ground reference for ADC and analog circuits, must be connected to VSS.
31 VREF- power_in Negative reference voltage for ADC, typically connected to VSSA.
32 VREF+ power_in Positive reference voltage for ADC and DAC, 2.4 to 3.6 V with 10 nF decoupling capacitor.
33 VDDA power_in Analog power supply 2.4 to 3.6 V for ADC, DAC, oscillators and PLL with 10 nF and 100 nF decoupling.
34 PA0-WKUP bidirectional GPIO Port A pin 0 with wakeup capability, alternate functions USART2_CTS, ADC123_IN0, TIM2_CH1_ETR, or TIM5_CH1.
35 PA1 bidirectional GPIO Port A pin 1, alternate functions USART2_RTS, ADC123_IN1, or TIM5_CH2.
36 PA2 bidirectional GPIO Port A pin 2, alternate functions USART2_TX, TIM5_CH3, ADC123_IN2, TIM9_CH1, or TIM2_CH3.
37 PA3 bidirectional GPIO Port A pin 3, alternate functions USART2_RX, TIM5_CH4, ADC123_IN3, or TIM9_CH2.
38 VSS_4 power_in Ground reference for analog and digital circuits.
39 VDD_4 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
40 PA4 bidirectional GPIO Port A pin 4, alternate functions SPI1_NSS chip select, USART2_CK, DAC_OUT1 analog output, or ADC12_IN4.
41 PA5 bidirectional GPIO Port A pin 5, alternate functions SPI1_SCK serial clock, DAC_OUT2 analog output, or ADC12_IN5.
42 PA6 bidirectional GPIO Port A pin 6, alternate functions SPI1_MISO, TIM8_BKIN, ADC12_IN6, TIM3_CH1, or TIM13_CH1; remap to TIM1_BKIN.
43 PA7 bidirectional GPIO Port A pin 7, alternate functions SPI1_MOSI, TIM8_CH1N, ADC12_IN7, TIM3_CH2, or TIM14_CH1; remap to TIM1_CH1N.
44 PC4 bidirectional GPIO Port C pin 4, alternate function ADC12_IN14 analog input.
45 PC5 bidirectional GPIO Port C pin 5, alternate function ADC12_IN15 analog input.
46 PB0 bidirectional GPIO Port B pin 0, alternate functions ADC12_IN8, TIM3_CH3, or TIM8_CH2N; remap to TIM1_CH2N.
47 PB1 bidirectional GPIO Port B pin 1, alternate functions ADC12_IN9, TIM3_CH4, or TIM8_CH3N; remap to TIM1_CH3N.
48 PB2 bidirectional GPIO Port B pin 2 with BOOT1 function (5 V tolerant), boot configuration pin.
49 PF11 bidirectional GPIO Port F pin 11, alternate function FSMC_NIOS16 control signal (5 V tolerant).
50 PF12 bidirectional GPIO Port F pin 12, alternate function FSMC_A6 address line (5 V tolerant).
51 VSS_6 power_in Ground reference for analog and digital circuits.
52 VDD_6 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
53 PF13 bidirectional GPIO Port F pin 13, alternate function FSMC_A7 address line (5 V tolerant).
54 PF14 bidirectional GPIO Port F pin 14, alternate function FSMC_A8 address line (5 V tolerant).
55 PF15 bidirectional GPIO Port F pin 15, alternate function FSMC_A9 address line (5 V tolerant).
56 PG0 bidirectional GPIO Port G pin 0, alternate function FSMC_A10 address line (5 V tolerant).
57 PG1 bidirectional GPIO Port G pin 1, alternate function FSMC_A11 address line (5 V tolerant).
58 PE7 bidirectional GPIO Port E pin 7, alternate functions FSMC_D4 data line or TIM1_ETR external trigger (5 V tolerant).
59 PE8 bidirectional GPIO Port E pin 8, alternate functions FSMC_D5 data line or TIM1_CH1N complementary output (5 V tolerant).
60 PE9 bidirectional GPIO Port E pin 9, alternate functions FSMC_D6 data line or TIM1_CH1 capture/compare output (5 V tolerant).
61 VSS_7 power_in Ground reference for analog and digital circuits.
62 VDD_7 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
63 PE10 bidirectional GPIO Port E pin 10, alternate functions FSMC_D7 data line or TIM1_CH2N complementary output (5 V tolerant).
64 PE11 bidirectional GPIO Port E pin 11, alternate functions FSMC_D8 data line or TIM1_CH2 capture/compare output (5 V tolerant).
65 PE12 bidirectional GPIO Port E pin 12, alternate functions FSMC_D9 data line or TIM1_CH3N complementary output (5 V tolerant).
66 PE13 bidirectional GPIO Port E pin 13, alternate functions FSMC_D10 data line or TIM1_CH3 capture/compare output (5 V tolerant).
67 PE14 bidirectional GPIO Port E pin 14, alternate functions FSMC_D11 data line or TIM1_CH4 capture/compare output (5 V tolerant).
68 PE15 bidirectional GPIO Port E pin 15, alternate functions FSMC_D12 data line or TIM1_BKIN break input (5 V tolerant).
69 PB10 bidirectional GPIO Port B pin 10, alternate functions I2C2_SCL clock line, USART3_TX, or TIM2_CH3 (5 V tolerant).
70 PB11 bidirectional GPIO Port B pin 11, alternate functions I2C2_SDA data line, USART3_RX, or TIM2_CH4 (5 V tolerant).
71 VSS_1 power_in Ground reference for analog and digital circuits.
72 VDD_1 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
73 PB12 bidirectional GPIO Port B pin 12, alternate functions SPI2_NSS chip select, I2S2_WS word select, I2C2_SMBA bus alert, USART3_CK, or TIM1_BKIN (5 V tolerant).
74 PB13 bidirectional GPIO Port B pin 13, alternate functions SPI2_SCK serial clock, I2S2_CK clock, or USART3_CTS flow control (5 V tolerant).
75 PB14 bidirectional GPIO Port B pin 14, alternate functions SPI2_MISO data input, TIM1_CH2N complementary output, USART3_RTS, or TIM12_CH1 (5 V tolerant).
76 PB15 bidirectional GPIO Port B pin 15, alternate functions SPI2_MOSI data output, I2S2_SD serial data, TIM1_CH3N, or TIM12_CH2 (5 V tolerant).
77 PD8 bidirectional GPIO Port D pin 8, alternate functions FSMC_D13 data line or USART3_TX (5 V tolerant).
78 PD9 bidirectional GPIO Port D pin 9, alternate functions FSMC_D14 data line or USART3_RX (5 V tolerant).
79 PD10 bidirectional GPIO Port D pin 10, alternate functions FSMC_D15 data line or USART3_CK clock (5 V tolerant).
80 PD11 bidirectional GPIO Port D pin 11, alternate functions FSMC_A16 address line or USART3_CTS flow control (5 V tolerant).
81 PD12 bidirectional GPIO Port D pin 12, alternate functions FSMC_A17 address line, TIM4_CH1, or USART3_RTS (5 V tolerant).
82 PD13 bidirectional GPIO Port D pin 13, alternate functions FSMC_A18 address line or TIM4_CH2 capture/compare (5 V tolerant).
83 VSS_8 power_in Ground reference for analog and digital circuits.
84 VDD_8 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
85 PD14 bidirectional GPIO Port D pin 14, alternate functions FSMC_D0 data line or TIM4_CH3 capture/compare (5 V tolerant).
86 PD15 bidirectional GPIO Port D pin 15, alternate functions FSMC_D1 data line or TIM4_CH4 capture/compare (5 V tolerant).
87 PG2 bidirectional GPIO Port G pin 2, alternate function FSMC_A12 address line (5 V tolerant).
88 PG3 bidirectional GPIO Port G pin 3, alternate function FSMC_A13 address line (5 V tolerant).
89 PG4 bidirectional GPIO Port G pin 4, alternate function FSMC_A14 address line (5 V tolerant).
90 PG5 bidirectional GPIO Port G pin 5, alternate function FSMC_A15 address line (5 V tolerant).
91 PG6 bidirectional GPIO Port G pin 6, alternate function FSMC_INT2 interrupt signal (5 V tolerant).
92 PG7 bidirectional GPIO Port G pin 7, alternate function FSMC_INT3 interrupt signal (5 V tolerant).
93 PG8 bidirectional GPIO Port G pin 8 general-purpose I/O (5 V tolerant).
94 VSS_9 power_in Ground reference for analog and digital circuits.
95 VDD_9 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
96 PC6 bidirectional GPIO Port C pin 6, alternate functions I2S2_MCK master clock, TIM8_CH1, SDIO_D6, or TIM3_CH1 (5 V tolerant).
97 PC7 bidirectional GPIO Port C pin 7, alternate functions I2S3_MCK master clock, TIM8_CH2, SDIO_D7, or TIM3_CH2 (5 V tolerant).
98 PC8 bidirectional GPIO Port C pin 8, alternate functions TIM8_CH3, SDIO_D0, or TIM3_CH3 (5 V tolerant).
99 PC9 bidirectional GPIO Port C pin 9, alternate functions TIM8_CH4, SDIO_D1, or TIM3_CH4 (5 V tolerant).
100 PA8 bidirectional GPIO Port A pin 8, alternate functions USART1_CK clock, TIM1_CH1, or MCO master clock output (5 V tolerant).
101 PA9 bidirectional GPIO Port A pin 9, alternate functions USART1_TX transmit or TIM1_CH2 capture/compare (5 V tolerant).
102 PA10 bidirectional GPIO Port A pin 10, alternate functions USART1_RX receive or TIM1_CH3 capture/compare (5 V tolerant).
103 PA11 bidirectional GPIO Port A pin 11, alternate functions USART1_CTS flow control, USB_DM data minus, CAN_RX, or TIM1_CH4 (5 V tolerant).
104 PA12 bidirectional GPIO Port A pin 12, alternate functions USART1_RTS flow control, USB_DP data plus, CAN_TX, or TIM1_ETR (5 V tolerant).
105 PA13 bidirectional GPIO Port A pin 13 with JTMS-SWDIO debug function (5 V tolerant), serial wire debug data I/O.
106 NC unconnected Not connected pin.
107 VSS_2 power_in Ground reference for analog and digital circuits.
108 VDD_2 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
109 PA14 bidirectional GPIO Port A pin 14 with JTCK-SWCLK debug function (5 V tolerant), serial wire debug clock output.
110 PA15 bidirectional GPIO Port A pin 15 with JTDI debug function, alternate functions SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, or SPI1_NSS (5 V tolerant).
111 PC10 bidirectional GPIO Port C pin 10, alternate functions UART4_TX, SDIO_D2, or USART3_TX (5 V tolerant).
112 PC11 bidirectional GPIO Port C pin 11, alternate functions UART4_RX, SDIO_D3, or USART3_RX (5 V tolerant).
113 PC12 bidirectional GPIO Port C pin 12, alternate functions UART5_TX, SDIO_CK, or USART3_CK (5 V tolerant).
114 PD0 bidirectional GPIO Port D pin 0, alternate functions FSMC_D2 data line or CAN_RX; can be remapped from OSC_IN (5 V tolerant).
115 PD1 bidirectional GPIO Port D pin 1, alternate functions FSMC_D3 data line or CAN_TX; can be remapped from OSC_OUT (5 V tolerant).
116 PD2 bidirectional GPIO Port D pin 2, alternate functions TIM3_ETR external trigger, UART5_RX, or SDIO_CMD (5 V tolerant).
117 PD3 bidirectional GPIO Port D pin 3, alternate functions FSMC_CLK clock or USART2_CTS (5 V tolerant).
118 PD4 bidirectional GPIO Port D pin 4, alternate functions FSMC_NOE output enable or USART2_RTS (5 V tolerant).
119 PD5 bidirectional GPIO Port D pin 5, alternate functions FSMC_NWE write enable or USART2_TX (5 V tolerant).
120 VSS_10 power_in Ground reference for analog and digital circuits.
121 VDD_10 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
122 PD6 bidirectional GPIO Port D pin 6, alternate functions FSMC_NWAIT wait input or USART2_RX (5 V tolerant).
123 PD7 bidirectional GPIO Port D pin 7, alternate functions FSMC_NE1/FSMC_NCE2 chip enable or USART2_CK (5 V tolerant).
124 PG9 bidirectional GPIO Port G pin 9, alternate function FSMC_NE2/FSMC_NCE3 chip enable (5 V tolerant).
125 PG10 bidirectional GPIO Port G pin 10, alternate function FSMC_NCE4_1/FSMC_NE3 chip enable (5 V tolerant).
126 PG11 bidirectional GPIO Port G pin 11, alternate function FSMC_NCE4_2 chip enable (5 V tolerant).
127 PG12 bidirectional GPIO Port G pin 12, alternate function FSMC_NE4 chip enable (5 V tolerant).
128 PG13 bidirectional GPIO Port G pin 13, alternate function FSMC_A24 address line (5 V tolerant).
129 PG14 bidirectional GPIO Port G pin 14, alternate function FSMC_A25 address line (5 V tolerant).
130 VSS_11 power_in Ground reference for analog and digital circuits.
131 VDD_11 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.
132 PG15 bidirectional GPIO Port G pin 15 general-purpose I/O (5 V tolerant).
133 PB3 bidirectional GPIO Port B pin 3 with JTDO debug function, alternate functions SPI3_SCK, I2S3_CK, TIM2_CH2, or SPI1_SCK (5 V tolerant).
134 PB4 bidirectional GPIO Port B pin 4 with NJTRST debug function, alternate functions SPI3_MISO or SPI1_MISO (5 V tolerant).
135 PB5 bidirectional GPIO Port B pin 5, alternate functions I2C1_SMBA bus alert, SPI3_MOSI, I2S3_SD, TIM3_CH2, or SPI1_MOSI.
136 PB6 bidirectional GPIO Port B pin 6, alternate functions I2C1_SCL clock line, TIM4_CH1, or USART1_TX (5 V tolerant).
137 PB7 bidirectional GPIO Port B pin 7, alternate functions I2C1_SDA data line, FSMC_NADV advanced signal, TIM4_CH2, or USART1_RX (5 V tolerant).
138 BOOT0 input Boot configuration pin selects boot source: Flash memory bank 1, system memory, or SRAM.
139 PB8 bidirectional GPIO Port B pin 8, alternate functions TIM4_CH3, SDIO_D4, TIM10_CH1, I2C1_SCL, or CAN_RX (5 V tolerant).
140 PB9 bidirectional GPIO Port B pin 9, alternate functions TIM4_CH4, SDIO_D5, TIM11_CH1, I2C1_SDA, or CAN_TX (5 V tolerant).
141 PE0 bidirectional GPIO Port E pin 0, alternate functions TIM4_ETR or FSMC_NBL0 byte lane (5 V tolerant).
142 PE1 bidirectional GPIO Port E pin 1, alternate function FSMC_NBL1 byte lane (5 V tolerant).
143 VSS_3 power_in Ground reference for analog and digital circuits.
144 VDD_3 power_in Positive power supply 2.0 to 3.6 V for I/Os and internal logic.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: STM32F103ZGT6
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: stm32f103zgt6-etched.step / stm32f103zgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f103zgt6.step / stm32f103zgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (136 pp, sha256 69897f9cf77df3f0, retrieved 2026-09-25, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF