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STM32F103ZCH6
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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LFBGA-144. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownSTM32F103ZCH6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LFBGA-144
STM32F103ZCH6 from STMicroelectronics, in a LFBGA-144. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | PC13-TAMPER-RTC | bidirectional | I/O pin PC13, supplied through the power switch; limited to 3 mA sink, output speed at most 2 MHz with 30 pF load, and must not source current such as driving an LED. Alternate function TAMPER-RTC. |
| A2 | PE3 | bidirectional | 5 V tolerant (FT) I/O pin PE3; alternate functions TRACED0 and FSMC_A19. |
| A3 | PE2 | bidirectional | 5 V tolerant (FT) I/O pin PE2; alternate functions TRACECK and FSMC_A23. |
| A4 | PE1 | bidirectional | 5 V tolerant (FT) I/O pin PE1; alternate function FSMC_NBL1. |
| A5 | PE0 | bidirectional | 5 V tolerant (FT) I/O pin PE0; alternate functions TIM4_ETR and FSMC_NBL0. |
| A6 | PB4 | bidirectional | 5 V tolerant (FT) I/O pin PB4 (default NJTRST); remap functions SPI3_MISO, TIM3_CH1 and SPI1_MISO. |
| A7 | PB3 | bidirectional | 5 V tolerant (FT) I/O pin PB3 (default JTDO); remap functions SPI3_SCK/I2S3_CK, TRACESWO, TIM2_CH2 and SPI1_SCK. |
| A8 | PD6 | bidirectional | 5 V tolerant (FT) I/O pin PD6; alternate functions FSMC_NWAIT and USART2_RX. |
| A9 | PD7 | bidirectional | 5 V tolerant (FT) I/O pin PD7; alternate functions FSMC_NE1/FSMC_NCE2 and USART2_CK. |
| A10 | PA15 | bidirectional | 5 V tolerant (FT) I/O pin PA15 (default JTDI); alternate functions SPI3_NSS/I2S3_WS, TIM2_CH1_ETR and SPI1_NSS. |
| A11 | PA14 | bidirectional | 5 V tolerant (FT) I/O pin PA14 (default JTCK-SWCLK). |
| A12 | PA13 | bidirectional | 5 V tolerant (FT) I/O pin PA13 (default JTMS-SWDIO). |
| B1 | PC14-OSC32_IN | bidirectional | I/O pin PC14, supplied through the power switch; limited to 3 mA sink, output speed at most 2 MHz with 30 pF load, and must not source current. Main function OSC32_IN after backup-domain power-up. |
| B2 | PE4 | bidirectional | 5 V tolerant (FT) I/O pin PE4; alternate functions TRACED1 and FSMC_A20. |
| B3 | PE5 | bidirectional | 5 V tolerant (FT) I/O pin PE5; alternate functions TRACED2 and FSMC_A21. |
| B4 | PE6 | bidirectional | 5 V tolerant (FT) I/O pin PE6; alternate functions TRACED3 and FSMC_A22. |
| B5 | PB9 | bidirectional | 5 V tolerant (FT) I/O pin PB9; alternate functions TIM4_CH4, SDIO_D5, I2C1_SDA and CAN_TX. |
| B6 | PB5 | bidirectional | I/O pin PB5 (no FT marking in Table 5); alternate functions I2C1_SMBA, SPI3_MOSI/I2S3_SD, TIM3_CH2 and SPI1_MOSI. |
| B7 | PG15 | bidirectional | 5 V tolerant (FT) I/O pin PG15 with no alternate function listed. |
| B8 | PG12 | bidirectional | 5 V tolerant (FT) I/O pin PG12; alternate function FSMC_NE4. |
| B9 | PD5 | bidirectional | 5 V tolerant (FT) I/O pin PD5; alternate functions FSMC_NWE and USART2_TX. |
| B10 | PC11 | bidirectional | 5 V tolerant (FT) I/O pin PC11; alternate functions UART4_RX, SDIO_D3 and USART3_RX. |
| B11 | PC10 | bidirectional | 5 V tolerant (FT) I/O pin PC10; alternate functions UART4_TX, SDIO_D2 and USART3_TX. |
| B12 | PA12 | bidirectional | 5 V tolerant (FT) I/O pin PA12; alternate functions USART1_RTS, USBDP, CAN_TX and TIM1_ETR. |
| C1 | PC15-OSC32_OUT | bidirectional | I/O pin PC15, supplied through the power switch; limited to 3 mA sink, output speed at most 2 MHz with 30 pF load, and must not source current. Main function OSC32_OUT after backup-domain power-up. |
| C2 | VBAT | power_in | Backup-domain supply pin for the RTC and backup registers. |
| C3 | PF0 | bidirectional | 5 V tolerant (FT) I/O pin PF0; alternate function FSMC_A0. |
| C4 | PF1 | bidirectional | 5 V tolerant (FT) I/O pin PF1; alternate function FSMC_A1. |
| C5 | PB8 | bidirectional | 5 V tolerant (FT) I/O pin PB8; alternate functions TIM4_CH3, SDIO_D4, I2C1_SCL and CAN_RX. |
| C6 | PB6 | bidirectional | 5 V tolerant (FT) I/O pin PB6; alternate functions I2C1_SCL, TIM4_CH1 and USART1_TX. |
| C7 | PG14 | bidirectional | 5 V tolerant (FT) I/O pin PG14; alternate function FSMC_A25. |
| C8 | PG11 | bidirectional | 5 V tolerant (FT) I/O pin PG11; alternate function FSMC_NCE4_2. |
| C9 | PD4 | bidirectional | 5 V tolerant (FT) I/O pin PD4; alternate functions FSMC_NOE and USART2_RTS. |
| C10 | PC12 | bidirectional | 5 V tolerant (FT) I/O pin PC12; alternate functions UART5_TX, SDIO_CK and USART3_CK. |
| C11 | NC | unconnected | Ball C11 is not connected (Table 5 'Not connected'). |
| C12 | PA11 | bidirectional | 5 V tolerant (FT) I/O pin PA11; alternate functions USART1_CTS, USBDM, CAN_RX and TIM1_CH4. |
| D1 | OSC_IN | input | External 4 to 16 MHz crystal oscillator input (HSE). |
| D2 | VSS_5 | power_in | Digital ground pin. |
| D3 | VDD_5 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| D4 | PF2 | bidirectional | 5 V tolerant (FT) I/O pin PF2; alternate function FSMC_A2. |
| D5 | BOOT0 | input | Boot pin BOOT0 selects the boot mode (input). |
| D6 | PB7 | bidirectional | 5 V tolerant (FT) I/O pin PB7; alternate functions I2C1_SDA, FSMC_NADV and TIM4_CH2 (USART1_RX remap). |
| D7 | PG13 | bidirectional | 5 V tolerant (FT) I/O pin PG13; alternate function FSMC_A24. |
| D8 | PG10 | bidirectional | 5 V tolerant (FT) I/O pin PG10; alternate functions FSMC_NCE4_1 and FSMC_NE3. |
| D9 | PD3 | bidirectional | 5 V tolerant (FT) I/O pin PD3; alternate functions FSMC_CLK and USART2_CTS. |
| D10 | PD1 | bidirectional | 5 V tolerant (FT) I/O pin PD1; alternate functions OSC_OUT (on this package PD1 is available by default), FSMC_D3 and CAN_TX. |
| D11 | PA10 | bidirectional | 5 V tolerant (FT) I/O pin PA10; alternate functions USART1_RX and TIM1_CH3. |
| D12 | PA9 | bidirectional | 5 V tolerant (FT) I/O pin PA9; alternate functions USART1_TX and TIM1_CH2. |
| E1 | OSC_OUT | output | Output of the external 4 to 16 MHz crystal oscillator (HSE). |
| E2 | PF3 | bidirectional | I/O pin PF3 (no FT marking in Table 5); alternate function FSMC_A3. |
| E3 | PF4 | bidirectional | I/O pin PF4 (no FT marking in Table 5); alternate function FSMC_A4. |
| E4 | PF5 | bidirectional | I/O pin PF5 (no FT marking in Table 5); alternate function FSMC_A5. |
| E5 | VSS_3 | power_in | Digital ground pin. |
| E6 | VSS_11 | power_in | Digital ground pin. |
| E7 | VSS_10 | power_in | Digital ground pin. |
| E8 | PG9 | bidirectional | 5 V tolerant (FT) I/O pin PG9; alternate functions FSMC_NE2 and FSMC_NCE3. |
| E9 | PD2 | bidirectional | 5 V tolerant (FT) I/O pin PD2; alternate functions TIM3_ETR, UART5_RX and SDIO_CMD. |
| E10 | PD0 | bidirectional | 5 V tolerant (FT) I/O pin PD0; alternate functions FSMC_D2 and CAN_RX (available by default on this package, no remap needed). |
| E11 | PC9 | bidirectional | 5 V tolerant (FT) I/O pin PC9; alternate functions TIM8_CH4, SDIO_D1 and TIM3_CH4. |
| E12 | PA8 | bidirectional | 5 V tolerant (FT) I/O pin PA8; alternate functions USART1_CK, TIM1_CH1 and MCO. |
| F1 | NRST | bidirectional | Reset pin NRST (I/O); see section 5.3.15 for the NRST pin characteristics. |
| F2 | PF7 | bidirectional | I/O pin PF7 (no FT marking in Table 5); alternate functions ADC3_IN5 and FSMC_NREG. |
| F3 | PF6 | bidirectional | I/O pin PF6 (no FT marking in Table 5); alternate functions ADC3_IN4 and FSMC_NIORD. |
| F4 | VDD_4 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| F5 | VDD_3 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| F6 | VDD_11 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| F7 | VDD_10 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| F8 | VDD_8 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| F9 | VDD_2 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| F10 | VDD_9 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| F11 | PC8 | bidirectional | 5 V tolerant (FT) I/O pin PC8; alternate functions TIM8_CH3, SDIO_D0 and TIM3_CH3. |
| F12 | PC7 | bidirectional | 5 V tolerant (FT) I/O pin PC7; alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7 and TIM3_CH2. |
| G1 | PF10 | bidirectional | I/O pin PF10 (no FT marking in Table 5); alternate functions ADC3_IN8 and FSMC_INTR. |
| G2 | PF9 | bidirectional | I/O pin PF9 (no FT marking in Table 5); alternate functions ADC3_IN7 and FSMC_CD. |
| G3 | PF8 | bidirectional | I/O pin PF8 (no FT marking in Table 5); alternate functions ADC3_IN6 and FSMC_NIOWR. |
| G4 | VSS_4 | power_in | Digital ground pin. |
| G5 | VDD_6 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| G6 | VDD_7 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| G7 | VDD_1 | power_in | Digital supply pin (2.0 to 3.6 V application supply and I/Os). |
| G8 | VSS_8 | power_in | Digital ground pin. |
| G9 | VSS_2 | power_in | Digital ground pin. |
| G10 | VSS_9 | power_in | Digital ground pin. |
| G11 | PG8 | bidirectional | 5 V tolerant (FT) I/O pin PG8 with no alternate function listed. |
| G12 | PC6 | bidirectional | 5 V tolerant (FT) I/O pin PC6; alternate functions I2S2_MCK, TIM8_CH1, SDIO_D6 and TIM3_CH1. |
| H1 | PC0 | bidirectional | I/O pin PC0 (no FT marking in Table 5); alternate function ADC123_IN10. |
| H2 | PC1 | bidirectional | I/O pin PC1 (no FT marking in Table 5); alternate function ADC123_IN11. |
| H3 | PC2 | bidirectional | I/O pin PC2 (no FT marking in Table 5); alternate function ADC123_IN12. |
| H4 | PC3 | bidirectional | I/O pin PC3 (no FT marking in Table 5); alternate function ADC123_IN13. |
| H5 | VSS_6 | power_in | Digital ground pin. |
| H6 | VSS_7 | power_in | Digital ground pin. |
| H7 | VSS_1 | power_in | Digital ground pin. |
| H8 | PE11 | bidirectional | 5 V tolerant (FT) I/O pin PE11; alternate functions FSMC_D8 and TIM1_CH2. |
| H9 | PD11 | bidirectional | 5 V tolerant (FT) I/O pin PD11; alternate functions FSMC_A16 and USART3_CTS. |
| H10 | PG7 | bidirectional | 5 V tolerant (FT) I/O pin PG7; alternate function FSMC_INT3. |
| H11 | PG6 | bidirectional | 5 V tolerant (FT) I/O pin PG6; alternate function FSMC_INT2. |
| H12 | PG5 | bidirectional | 5 V tolerant (FT) I/O pin PG5; alternate function FSMC_A15. |
| J1 | VSSA | power_in | Analog ground pin for the ADC and DAC. |
| J2 | PA0-WKUP | bidirectional | I/O pin PA0; alternate functions WKUP, USART2_CTS, ADC123_IN0, TIM2_CH1_ETR and TIM5_CH1/TIM8_ETR. |
| J3 | PA4 | bidirectional | I/O pin PA4; alternate functions SPI1_NSS, USART2_CK and DAC_OUT1/ADC12_IN4. |
| J4 | PC4 | bidirectional | I/O pin PC4 (no FT marking in Table 5); alternate function ADC12_IN14. |
| J5 | PB2/BOOT1 | bidirectional | 5 V tolerant (FT) I/O pin PB2, shared with the BOOT1 boot-mode select function. |
| J6 | PG1 | bidirectional | 5 V tolerant (FT) I/O pin PG1; alternate function FSMC_A11. |
| J7 | PE10 | bidirectional | 5 V tolerant (FT) I/O pin PE10; alternate functions FSMC_D7 and TIM1_CH2N. |
| J8 | PE12 | bidirectional | 5 V tolerant (FT) I/O pin PE12; alternate functions FSMC_D9 and TIM1_CH3N. |
| J9 | PD10 | bidirectional | 5 V tolerant (FT) I/O pin PD10; alternate functions FSMC_D15 and USART3_CK. |
| J10 | PG4 | bidirectional | 5 V tolerant (FT) I/O pin PG4; alternate function FSMC_A14. |
| J11 | PG3 | bidirectional | 5 V tolerant (FT) I/O pin PG3; alternate function FSMC_A13. |
| J12 | PG2 | bidirectional | 5 V tolerant (FT) I/O pin PG2; alternate function FSMC_A12. |
| K1 | VREF- | power_in | Negative ADC reference voltage, tied to 0 V (VSSA). |
| K2 | PA1 | bidirectional | I/O pin PA1; alternate functions USART2_RTS, ADC123_IN1, TIM5_CH2 and TIM2_CH2. |
| K3 | PA5 | bidirectional | I/O pin PA5; alternate functions SPI1_SCK, DAC_OUT2 and ADC12_IN5. |
| K4 | PC5 | bidirectional | I/O pin PC5 (no FT marking in Table 5); alternate function ADC12_IN15. |
| K5 | PF13 | bidirectional | 5 V tolerant (FT) I/O pin PF13; alternate function FSMC_A7. |
| K6 | PG0 | bidirectional | 5 V tolerant (FT) I/O pin PG0; alternate function FSMC_A10. |
| K7 | PE9 | bidirectional | 5 V tolerant (FT) I/O pin PE9; alternate functions FSMC_D6 and TIM1_CH1. |
| K8 | PE13 | bidirectional | 5 V tolerant (FT) I/O pin PE13; alternate functions FSMC_D10 and TIM1_CH3. |
| K9 | PD9 | bidirectional | 5 V tolerant (FT) I/O pin PD9; alternate functions FSMC_D14 and USART3_RX. |
| K10 | PD13 | bidirectional | 5 V tolerant (FT) I/O pin PD13; alternate functions FSMC_A18 and TIM4_CH2. |
| K11 | PD14 | bidirectional | 5 V tolerant (FT) I/O pin PD14; alternate functions FSMC_D0 and TIM4_CH3. |
| K12 | PD15 | bidirectional | 5 V tolerant (FT) I/O pin PD15; alternate functions FSMC_D1 and TIM4_CH4. |
| L1 | VREF+ | power_in | Positive ADC reference voltage, 2.4 V to VDDA. |
| L2 | PA2 | bidirectional | I/O pin PA2; alternate functions USART2_TX, TIM5_CH3 and ADC123_IN2/TIM2_CH3. |
| L3 | PA6 | bidirectional | I/O pin PA6; alternate functions SPI1_MISO, TIM8_BKIN, ADC12_IN6, TIM3_CH1 and TIM1_BKIN. |
| L4 | PB0 | bidirectional | I/O pin PB0; alternate functions ADC12_IN8, TIM3_CH3, TIM8_CH2N and TIM1_CH2N. |
| L5 | PF12 | bidirectional | I/O pin PF12 (no FT marking in Table 5); alternate function FSMC_A6. |
| L6 | PF15 | bidirectional | 5 V tolerant (FT) I/O pin PF15; alternate function FSMC_A9. |
| L7 | PE8 | bidirectional | 5 V tolerant (FT) I/O pin PE8; alternate functions FSMC_D5 and TIM1_CH1N. |
| L8 | PE14 | bidirectional | 5 V tolerant (FT) I/O pin PE14; alternate functions FSMC_D11 and TIM1_CH4. |
| L9 | PD8 | bidirectional | 5 V tolerant (FT) I/O pin PD8; alternate functions FSMC_D13 and USART3_TX. |
| L10 | PD12 | bidirectional | 5 V tolerant (FT) I/O pin PD12; alternate functions FSMC_A17, TIM4_CH1 and USART3_RTS. |
| L11 | PB14 | bidirectional | 5 V tolerant (FT) I/O pin PB14; alternate functions SPI2_MISO, TIM1_CH2N and USART3_RTS. |
| L12 | PB15 | bidirectional | 5 V tolerant (FT) I/O pin PB15; alternate functions SPI2_MOSI, I2S2_SD and TIM1_CH3N. |
| M1 | VDDA | power_in | Analog supply pin for the ADC and DAC; ADC VDDA range is 2.4 to 3.6 V. |
| M2 | PA3 | bidirectional | I/O pin PA3; alternate functions USART2_RX, TIM5_CH4 and ADC123_IN3/TIM2_CH4. |
| M3 | PA7 | bidirectional | I/O pin PA7; alternate functions SPI1_MOSI, TIM8_CH1N, ADC12_IN7, TIM3_CH2 and TIM1_CH1N. |
| M4 | PB1 | bidirectional | I/O pin PB1; alternate functions ADC12_IN9, TIM3_CH4, TIM8_CH3N and TIM1_CH3N. |
| M5 | PF11 | bidirectional | 5 V tolerant (FT) I/O pin PF11; alternate function FSMC_NIOS16. |
| M6 | PF14 | bidirectional | 5 V tolerant (FT) I/O pin PF14; alternate function FSMC_A8. |
| M7 | PE7 | bidirectional | 5 V tolerant (FT) I/O pin PE7; alternate functions FSMC_D4 and TIM1_ETR. |
| M8 | PE15 | bidirectional | 5 V tolerant (FT) I/O pin PE15; alternate functions FSMC_D12 and TIM1_BKIN. |
| M9 | PB10 | bidirectional | 5 V tolerant (FT) I/O pin PB10; alternate functions I2C2_SCL, USART3_TX and TIM2_CH3. |
| M10 | PB11 | bidirectional | 5 V tolerant (FT) I/O pin PB11; alternate functions I2C2_SDA, USART3_RX and TIM2_CH4. |
| M11 | PB12 | bidirectional | 5 V tolerant (FT) I/O pin PB12; alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK and TIM1_BKIN. |
| M12 | PB13 | bidirectional | 5 V tolerant (FT) I/O pin PB13; alternate functions SPI2_SCK, I2S2_CK, USART3_CTS and TIM1_CH1N. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LFBGA-144 |
| Category | Embedded Processors & Controllers |
| Pins | 144 |
CAD (KiCad official)
- Symbol:
STM32F103ZCH6 - Footprint:
Package_BGA:LFBGA-144_10x10mm_Layout12x12_P0.8mm - 3D model: LFBGA-144 (KiCad packages3D, STEP)
- 3D model files:
stm32f103zch6-etched.step/stm32f103zch6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f103zch6.step/stm32f103zch6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (143 pp, sha256
c61db5e362b62f2f, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).