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STM32F103VET7
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F103VET7
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
STM32F103VET7 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V tolerant (FT) I/O; default function PE2, alternates TRACECK and FSMC_A23. |
| 2 | PE3 | bidirectional | 5 V tolerant (FT) I/O; default function PE3, alternates TRACED0 and FSMC_A19. |
| 3 | PE4 | bidirectional | 5 V tolerant (FT) I/O; default function PE4, alternates TRACED1 and FSMC_A20. |
| 4 | PE5 | bidirectional | 5 V tolerant (FT) I/O; default function PE5, alternates TRACED2 and FSMC_A21. |
| 5 | PE6 | bidirectional | 5 V tolerant (FT) I/O; default function PE6, alternates TRACED3 and FSMC_A22. |
| 6 | VBAT | power_in | Backup-domain supply for the RTC and backup registers. |
| 7 | PC13-TAMPER-RTC | bidirectional | I/O (not 5 V tolerant) supplied through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz with 30 pF max load and it must not source current such as an LED drive. |
| 8 | PC14-OSC32_IN | bidirectional | I/O (not 5 V tolerant) supplied through the power switch, limited to 3 mA sink, 2 MHz at 30 pF max, and not usable as a current source; alternate function OSC32_IN. |
| 9 | PC15-OSC32_OUT | bidirectional | I/O (not 5 V tolerant) supplied through the power switch, limited to 3 mA sink, 2 MHz at 30 pF max, and not usable as a current source; alternate function OSC32_OUT. |
| 10 | VSS_5 | power_in | Digital ground pin for the device. |
| 11 | VDD_5 | power_in | Digital supply pin; application supply and I/Os range 2.0 to 3.6 V. |
| 12 | OSC_IN | input | Input of the 4 to 16 MHz crystal oscillator (HSE). |
| 13 | OSC_OUT | output | Output of the 4 to 16 MHz crystal oscillator (HSE). |
| 14 | NRST | bidirectional | Device reset pin; electrical characteristics are given in Section 5.3.15 NRST pin characteristics. |
| 15 | PC0 | bidirectional | I/O (not 5 V tolerant); default function PC0, alternate ADC123_IN10. |
| 16 | PC1 | bidirectional | I/O (not 5 V tolerant); default function PC1, alternate ADC123_IN11. |
| 17 | PC2 | bidirectional | I/O (not 5 V tolerant); default function PC2, alternate ADC123_IN12. |
| 18 | PC3 | bidirectional | I/O (not 5 V tolerant); default function PC3, alternate ADC123_IN13. |
| 19 | VSSA | power_in | Analog ground pin for the ADC and DAC. |
| 20 | VREF- | power_in | Negative ADC reference voltage input; specified as 0 V in the ADC characteristics (Table 59). |
| 21 | VREF+ | power_in | Positive ADC reference voltage input; range 2.4 V to VDDA (Table 59). |
| 22 | VDDA | power_in | Analog supply for the ADC and DAC; range 2.4 to 3.6 V for ADC (Table 59). |
| 23 | PA0-WKUP | bidirectional | I/O (not 5 V tolerant); default function PA0-WKUP, alternates USART2_CTS, ADC123_IN0, TIM2_CH1_ETR and TIM5_CH1/TIM8_ETR. |
| 24 | PA1 | bidirectional | I/O (not 5 V tolerant); default function PA1, alternates USART2_RTS, ADC123_IN1, TIM5_CH2 and TIM2_CH2. |
| 25 | PA2 | bidirectional | I/O (not 5 V tolerant); default function PA2, alternates USART2_TX, TIM5_CH3, ADC123_IN2 and TIM2_CH3. |
| 26 | PA3 | bidirectional | I/O (not 5 V tolerant); default function PA3, alternates USART2_RX, TIM5_CH4, ADC123_IN3 and TIM2_CH4. |
| 27 | VSS_4 | power_in | Digital ground pin for the device. |
| 28 | VDD_4 | power_in | Digital supply pin; application supply and I/Os range 2.0 to 3.6 V. |
| 29 | PA4 | bidirectional | I/O (not 5 V tolerant); default function PA4, alternates SPI1_NSS, USART2_CK, DAC_OUT1 and ADC12_IN4. |
| 30 | PA5 | bidirectional | I/O (not 5 V tolerant); default function PA5, alternates SPI1_SCK, DAC_OUT2 and ADC12_IN5. |
| 31 | PA6 | bidirectional | I/O (not 5 V tolerant); default function PA6, alternates SPI1_MISO, TIM8_BKIN, ADC12_IN6, TIM3_CH1 and TIM1_BKIN. |
| 32 | PA7 | bidirectional | I/O (not 5 V tolerant); default function PA7, alternates SPI1_MOSI, TIM8_CH1N, ADC12_IN7, TIM3_CH2 and TIM1_CH1N. |
| 33 | PC4 | bidirectional | I/O (not 5 V tolerant); default function PC4, alternate ADC12_IN14. |
| 34 | PC5 | bidirectional | I/O (not 5 V tolerant); default function PC5, alternate ADC12_IN15. |
| 35 | PB0 | bidirectional | I/O (not 5 V tolerant); default function PB0, alternates ADC12_IN8, TIM3_CH3, TIM8_CH2N and TIM1_CH2N. |
| 36 | PB1 | bidirectional | I/O (not 5 V tolerant); default function PB1, alternates ADC12_IN9, TIM3_CH4, TIM8_CH3N and TIM1_CH3N. |
| 37 | PB2/BOOT1 | bidirectional | 5 V tolerant (FT) I/O; default function PB2, shared with the BOOT1 boot-mode pin. |
| 38 | PE7 | bidirectional | 5 V tolerant (FT) I/O; default function PE7, alternates FSMC_D4 and TIM1_ETR. |
| 39 | PE8 | bidirectional | 5 V tolerant (FT) I/O; default function PE8, alternates FSMC_D5 and TIM1_CH1N. |
| 40 | PE9 | bidirectional | 5 V tolerant (FT) I/O; default function PE9, alternates FSMC_D6 and TIM1_CH1. |
| 41 | PE10 | bidirectional | 5 V tolerant (FT) I/O; default function PE10, alternates FSMC_D7 and TIM1_CH2N. |
| 42 | PE11 | bidirectional | 5 V tolerant (FT) I/O; default function PE11, alternates FSMC_D8 and TIM1_CH2. |
| 43 | PE12 | bidirectional | 5 V tolerant (FT) I/O; default function PE12, alternates FSMC_D9 and TIM1_CH3N. |
| 44 | PE13 | bidirectional | 5 V tolerant (FT) I/O; default function PE13, alternates FSMC_D10 and TIM1_CH3. |
| 45 | PE14 | bidirectional | 5 V tolerant (FT) I/O; default function PE14, alternates FSMC_D11 and TIM1_CH4. |
| 46 | PE15 | bidirectional | 5 V tolerant (FT) I/O; default function PE15, alternates FSMC_D12 and TIM1_BKIN. |
| 47 | PB10 | bidirectional | 5 V tolerant (FT) I/O; default function PB10, alternates I2C2_SCL, USART3_TX and TIM2_CH3. |
| 48 | PB11 | bidirectional | 5 V tolerant (FT) I/O; default function PB11, alternates I2C2_SDA, USART3_RX and TIM2_CH4. |
| 49 | VSS_1 | power_in | Digital ground pin for the device. |
| 50 | VDD_1 | power_in | Digital supply pin; application supply and I/Os range 2.0 to 3.6 V. |
| 51 | PB12 | bidirectional | 5 V tolerant (FT) I/O; default function PB12, alternates SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK and TIM1_BKIN. |
| 52 | PB13 | bidirectional | 5 V tolerant (FT) I/O; default function PB13, alternates SPI2_SCK/I2S2_CK, USART3_CTS and TIM1_CH1N. |
| 53 | PB14 | bidirectional | 5 V tolerant (FT) I/O; default function PB14, alternates SPI2_MISO, TIM1_CH2N and USART3_RTS. |
| 54 | PB15 | bidirectional | 5 V tolerant (FT) I/O; default function PB15, alternates SPI2_MOSI/I2S2_SD and TIM1_CH3N. |
| 55 | PD8 | bidirectional | 5 V tolerant (FT) I/O; default function PD8, alternates FSMC_D13 and USART3_TX. |
| 56 | PD9 | bidirectional | 5 V tolerant (FT) I/O; default function PD9, alternates FSMC_D14 and USART3_RX. |
| 57 | PD10 | bidirectional | 5 V tolerant (FT) I/O; default function PD10, alternates FSMC_D15 and USART3_CK. |
| 58 | PD11 | bidirectional | 5 V tolerant (FT) I/O; default function PD11, alternates FSMC_A16 and USART3_CTS. |
| 59 | PD12 | bidirectional | 5 V tolerant (FT) I/O; default function PD12, alternates FSMC_A17, TIM4_CH1 and USART3_RTS. |
| 60 | PD13 | bidirectional | 5 V tolerant (FT) I/O; default function PD13, alternates FSMC_A18 and TIM4_CH2. |
| 61 | PD14 | bidirectional | 5 V tolerant (FT) I/O; default function PD14, alternates FSMC_D0 and TIM4_CH3. |
| 62 | PD15 | bidirectional | 5 V tolerant (FT) I/O; default function PD15, alternates FSMC_D1 and TIM4_CH4. |
| 63 | PC6 | bidirectional | 5 V tolerant (FT) I/O; default function PC6, alternates I2S2_MCK, TIM8_CH1, SDIO_D6 and TIM3_CH1. |
| 64 | PC7 | bidirectional | 5 V tolerant (FT) I/O; default function PC7, alternates I2S3_MCK, TIM8_CH2, SDIO_D7 and TIM3_CH2. |
| 65 | PC8 | bidirectional | 5 V tolerant (FT) I/O; default function PC8, alternates TIM8_CH3, SDIO_D0 and TIM3_CH3. |
| 66 | PC9 | bidirectional | 5 V tolerant (FT) I/O; default function PC9, alternates TIM8_CH4, SDIO_D1 and TIM3_CH4. |
| 67 | PA8 | bidirectional | 5 V tolerant (FT) I/O; default function PA8, alternates USART1_CK, TIM1_CH1 and MCO. |
| 68 | PA9 | bidirectional | 5 V tolerant (FT) I/O; default function PA9, alternates USART1_TX and TIM1_CH2. |
| 69 | PA10 | bidirectional | 5 V tolerant (FT) I/O; default function PA10, alternates USART1_RX and TIM1_CH3. |
| 70 | PA11 | bidirectional | 5 V tolerant (FT) I/O; default function PA11, alternates USART1_CTS, USBDM, CAN_RX and TIM1_CH4. |
| 71 | PA12 | bidirectional | 5 V tolerant (FT) I/O; default function PA12, alternates USART1_RTS, USBDP, CAN_TX and TIM1_ETR. |
| 72 | PA13 | bidirectional | 5 V tolerant (FT) I/O; default function JTMS-SWDIO, the serial wire debug data pin. |
| 73 | NC | unconnected | Not connected on the LQFP100 package, as printed in Table 5. |
| 74 | VSS_2 | power_in | Digital ground pin for the device. |
| 75 | VDD_2 | power_in | Digital supply pin; application supply and I/Os range 2.0 to 3.6 V. |
| 76 | PA14 | bidirectional | 5 V tolerant (FT) I/O; default function JTCK-SWCLK, the serial wire debug clock pin. |
| 77 | PA15 | bidirectional | 5 V tolerant (FT) I/O; default function JTDI, alternates SPI3_NSS/I2S3_WS and TIM2_CH1_ETR, remap PA15/SPI1_NSS. |
| 78 | PC10 | bidirectional | 5 V tolerant (FT) I/O; default function PC10, alternates UART4_TX, SDIO_D2 and USART3_TX. |
| 79 | PC11 | bidirectional | 5 V tolerant (FT) I/O; default function PC11, alternates UART4_RX, SDIO_D3 and USART3_RX. |
| 80 | PC12 | bidirectional | 5 V tolerant (FT) I/O; default function PC12, alternates UART5_TX, SDIO_CK and USART3_CK. |
| 81 | PD0 | bidirectional | 5 V tolerant (FT) I/O; on LQFP100 PD0 is available by default, with alternates FSMC_D2 and CAN_RX. |
| 82 | PD1 | bidirectional | 5 V tolerant (FT) I/O; on LQFP100 PD1 is available by default, with alternates FSMC_D3 and CAN_TX. |
| 83 | PD2 | bidirectional | 5 V tolerant (FT) I/O; default function PD2, alternates TIM3_ETR, UART5_RX and SDIO_CMD. |
| 84 | PD3 | bidirectional | 5 V tolerant (FT) I/O; default function PD3, alternates FSMC_CLK and USART2_CTS. |
| 85 | PD4 | bidirectional | 5 V tolerant (FT) I/O; default function PD4, alternates FSMC_NOE and USART2_RTS. |
| 86 | PD5 | bidirectional | 5 V tolerant (FT) I/O; default function PD5, alternates FSMC_NWE and USART2_TX. |
| 87 | PD6 | bidirectional | 5 V tolerant (FT) I/O; default function PD6, alternates FSMC_NWAIT and USART2_RX. |
| 88 | PD7 | bidirectional | 5 V tolerant (FT) I/O; default function PD7, alternates FSMC_NE1/FSMC_NCE2 and USART2_CK. |
| 89 | PB3 | bidirectional | 5 V tolerant (FT) I/O; default function JTDO, alternates SPI3_SCK/I2S3_CK, TRACESWO, TIM2_CH2 and SPI1_SCK. |
| 90 | PB4 | bidirectional | 5 V tolerant (FT) I/O; default function NJTRST, alternates SPI3_MISO, TIM3_CH1 and SPI1_MISO. |
| 91 | PB5 | bidirectional | I/O (not 5 V tolerant); default function PB5, alternates I2C1_SMBA, SPI3_MOSI/I2S3_SD, TIM3_CH2 and SPI1_MOSI. |
| 92 | PB6 | bidirectional | 5 V tolerant (FT) I/O; default function PB6, alternates I2C1_SCL, TIM4_CH1 and USART1_TX. |
| 93 | PB7 | bidirectional | 5 V tolerant (FT) I/O; default function PB7, alternates I2C1_SDA, FSMC_NADV, TIM4_CH2 and USART1_RX. |
| 94 | BOOT0 | input | Boot mode selection input; boot modes are described in Section 2.3.10. |
| 95 | PB8 | bidirectional | 5 V tolerant (FT) I/O; default function PB8, alternates TIM4_CH3, SDIO_D4, I2C1_SCL and CAN_RX. |
| 96 | PB9 | bidirectional | 5 V tolerant (FT) I/O; default function PB9, alternates TIM4_CH4, SDIO_D5, I2C1_SDA and CAN_TX. |
| 97 | PE0 | bidirectional | 5 V tolerant (FT) I/O; default function PE0, alternates TIM4_ETR and FSMC_NBL0. |
| 98 | PE1 | bidirectional | 5 V tolerant (FT) I/O; default function PE1, alternate FSMC_NBL1. |
| 99 | VSS_3 | power_in | Digital ground pin for the device. |
| 100 | VDD_3 | power_in | Digital supply pin; application supply and I/Os range 2.0 to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
STM32F103VET7 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
stm32f103vet7-etched.step/stm32f103vet7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f103vet7.step/stm32f103vet7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (143 pp, sha256
c61db5e362b62f2f, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).