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STM32F103VCT6TR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f103vct6trfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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STM32F103VCT6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F103VCT6TR from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional Port E bit 2 GPIO or trace clock output; FSMC address A23 in multiplexed mode
2 PE3 bidirectional Port E bit 3 GPIO or trace data bit 0; FSMC address A19 in multiplexed mode
3 PE4 bidirectional Port E bit 4 GPIO or trace data bit 1; FSMC address A20 in multiplexed mode
4 PE5 bidirectional Port E bit 5 GPIO or trace data bit 2; FSMC address A21 in multiplexed mode
5 PE6 bidirectional Port E bit 6 GPIO or trace data bit 3; FSMC address A22 in multiplexed mode
6 VBAT power_in Battery backup supply voltage 1.8 to 3.6 V for RTC and backup registers
7 PC13-TAMPER-RTC bidirectional Port C bit 13 GPIO or RTC tamper input; 3 mA max output current
8 PC14-OSC32_IN bidirectional Port C bit 14 GPIO or 32.768 kHz oscillator input crystal pin
9 PC15-OSC32_OUT bidirectional Port C bit 15 GPIO or 32.768 kHz oscillator output crystal pin
10 PF0 bidirectional Port F bit 0 GPIO or FSMC address A0 pin
11 PF1 bidirectional Port F bit 1 GPIO or FSMC address A1 pin
12 PF2 bidirectional Port F bit 2 GPIO or FSMC address A2 pin
13 PF3 bidirectional Port F bit 3 GPIO or FSMC address A3 pin
14 PF4 bidirectional Port F bit 4 GPIO or FSMC address A4 pin
15 PF5 bidirectional Port F bit 5 GPIO or FSMC address A5 pin
16 VSS_5 power_in Ground supply 0 V
17 VDD_5 power_in Main digital supply voltage 2.0 to 3.6 V
18 PF6 bidirectional Port F bit 6 GPIO or ADC3 input channel 4; FSMC NIORD signal
19 PF7 bidirectional Port F bit 7 GPIO or ADC3 input channel 5; FSMC NREG signal
20 PF8 bidirectional Port F bit 8 GPIO or ADC3 input channel 6; FSMC NIOWR signal
21 PF9 bidirectional Port F bit 9 GPIO or ADC3 input channel 7; FSMC CD signal
22 PF10 bidirectional Port F bit 10 GPIO or ADC3 input channel 8; FSMC INTR signal
23 OSC_IN input External oscillator input for 4 to 16 MHz crystal or external clock signal
24 OSC_OUT output External oscillator output for 4 to 16 MHz crystal feedback
25 NRST bidirectional System reset input/output with internal pull-up; 100 ns noise filter
26 PC0 bidirectional Port C bit 0 GPIO or ADC123 input channel 10
27 PC1 bidirectional Port C bit 1 GPIO or ADC123 input channel 11
28 PC2 bidirectional Port C bit 2 GPIO or ADC123 input channel 12
29 PC3 bidirectional Port C bit 3 GPIO or ADC123 input channel 13; LQFP100 package PC3 not bonded
30 VSSA power_in Analog ground supply 0 V
31 VREF- power_in Negative ADC reference voltage 0 V
32 VREF+ power_in Positive ADC reference voltage 2.4 to VDDA V
33 VDDA power_in Analog supply voltage 2.4 to 3.6 V for ADC and reference
34 PA0-WKUP bidirectional Port A bit 0 GPIO with wakeup capability; USART2 CTS, ADC123 channel 0, TIM2 CH1/ETR
35 PA1 bidirectional Port A bit 1 GPIO; USART2 RTS, ADC123 channel 1, TIM2/TIM5 CH2
36 PA2 bidirectional Port A bit 2 GPIO; USART2 TX, ADC123 channel 2, TIM2/TIM5 CH3
37 PA3 bidirectional Port A bit 3 GPIO; USART2 RX, ADC123 channel 3, TIM2/TIM5 CH4
38 VSS_4 power_in Ground supply 0 V
39 VDD_4 power_in Main digital supply voltage 2.0 to 3.6 V
40 PA4 bidirectional Port A bit 4 GPIO; SPI1 NSS, USART2 CK, DAC output 1, ADC12 channel 4
41 PA5 bidirectional Port A bit 5 GPIO; SPI1 SCK, DAC output 2, ADC12 channel 5
42 PA6 bidirectional Port A bit 6 GPIO; SPI1 MISO, ADC12 channel 6, TIM1/TIM3 CH1
43 PA7 bidirectional Port A bit 7 GPIO; SPI1 MOSI, ADC12 channel 7, TIM1/TIM3 CH2
44 PC4 bidirectional Port C bit 4 GPIO or ADC12 input channel 14
45 PC5 bidirectional Port C bit 5 GPIO or ADC12 input channel 15
46 PB0 bidirectional Port B bit 0 GPIO; ADC12 channel 8, TIM1/TIM3/TIM8 CH
47 PB1 bidirectional Port B bit 1 GPIO; ADC12 channel 9, TIM1/TIM3/TIM8 CH
48 PB2 bidirectional Port B bit 2 GPIO or boot flash bank select BOOT1 pin; 5 V tolerant
49 PF11 bidirectional Port F bit 11 GPIO or FSMC NIOS16 signal; 5 V tolerant
50 PF12 bidirectional Port F bit 12 GPIO or FSMC address A6 pin; 5 V tolerant
51 VSS_6 power_in Ground supply 0 V
52 VDD_6 power_in Main digital supply voltage 2.0 to 3.6 V
53 PF13 bidirectional Port F bit 13 GPIO or FSMC address A7 pin; 5 V tolerant
54 PF14 bidirectional Port F bit 14 GPIO or FSMC address A8 pin; 5 V tolerant
55 PF15 bidirectional Port F bit 15 GPIO or FSMC address A9 pin; 5 V tolerant
56 PG0 bidirectional Port G bit 0 GPIO or FSMC address A10 pin; 5 V tolerant
57 PG1 bidirectional Port G bit 1 GPIO or FSMC address A11 pin; 5 V tolerant
58 PE7 bidirectional Port E bit 7 GPIO; FSMC data D4, TIM1 ETR; 5 V tolerant
59 PE8 bidirectional Port E bit 8 GPIO; FSMC data D5, TIM1 CH1N; 5 V tolerant
60 PE9 bidirectional Port E bit 9 GPIO; FSMC data D6, TIM1 CH1; 5 V tolerant
61 VSS_7 power_in Ground supply 0 V
62 VDD_7 power_in Main digital supply voltage 2.0 to 3.6 V
63 PE10 bidirectional Port E bit 10 GPIO; FSMC data D7, TIM1 CH2N; 5 V tolerant
64 PE11 bidirectional Port E bit 11 GPIO; FSMC data D8, TIM1 CH2; 5 V tolerant
65 PE12 bidirectional Port E bit 12 GPIO; FSMC data D9, TIM1 CH3N; 5 V tolerant
66 PE13 bidirectional Port E bit 13 GPIO; FSMC data D10, TIM1 CH3; 5 V tolerant
67 PE14 bidirectional Port E bit 14 GPIO; FSMC data D11, TIM1 CH4; 5 V tolerant
68 PE15 bidirectional Port E bit 15 GPIO; FSMC data D12, TIM1 BKIN; 5 V tolerant
69 PB10 bidirectional Port B bit 10 GPIO; I2C2 SCL, USART3 TX, TIM2 CH3; 5 V tolerant
70 PB11 bidirectional Port B bit 11 GPIO; I2C2 SDA, USART3 RX, TIM2 CH4; 5 V tolerant
71 VSS_1 power_in Ground supply 0 V
72 VDD_1 power_in Main digital supply voltage 2.0 to 3.6 V
73 PB12 bidirectional Port B bit 12 GPIO; SPI2 NSS, I2S2 WS, I2C2 SMBA, USART3 CK, TIM1 BKIN; 5 V tolerant
74 PB13 bidirectional Port B bit 13 GPIO; SPI2 SCK, I2S2 CK, USART3 CTS, TIM1 CH1N; 5 V tolerant
75 PB14 bidirectional Port B bit 14 GPIO; SPI2 MISO, TIM1 CH2N, USART3 RTS; 5 V tolerant
76 PB15 bidirectional Port B bit 15 GPIO; SPI2 MOSI, I2S2 SD, TIM1 CH3N; 5 V tolerant
77 PD8 bidirectional Port D bit 8 GPIO; FSMC data D13, USART3 TX; 5 V tolerant
78 PD9 bidirectional Port D bit 9 GPIO; FSMC data D14, USART3 RX; 5 V tolerant
79 PD10 bidirectional Port D bit 10 GPIO; FSMC data D15, USART3 CK; 5 V tolerant
80 PD11 bidirectional Port D bit 11 GPIO; FSMC address A16, USART3 CTS; 5 V tolerant
81 PD12 bidirectional Port D bit 12 GPIO; FSMC address A17, TIM4 CH1, USART3 RTS; 5 V tolerant
82 PD13 bidirectional Port D bit 13 GPIO; FSMC address A18, TIM4 CH2; 5 V tolerant
83 VSS_8 power_in Ground supply 0 V
84 VDD_8 power_in Main digital supply voltage 2.0 to 3.6 V
85 PD14 bidirectional Port D bit 14 GPIO; FSMC data D0, TIM4 CH3; 5 V tolerant
86 PD15 bidirectional Port D bit 15 GPIO; FSMC data D1, TIM4 CH4; 5 V tolerant
87 PG2 bidirectional Port G bit 2 GPIO or FSMC address A12 pin; 5 V tolerant
88 PG3 bidirectional Port G bit 3 GPIO or FSMC address A13 pin; 5 V tolerant
89 PG4 bidirectional Port G bit 4 GPIO or FSMC address A14 pin; 5 V tolerant
90 PG5 bidirectional Port G bit 5 GPIO or FSMC address A15 pin; 5 V tolerant
91 PG6 bidirectional Port G bit 6 GPIO or FSMC interrupt INT2 signal; 5 V tolerant
92 PG7 bidirectional Port G bit 7 GPIO or FSMC interrupt INT3 signal; 5 V tolerant
93 PG8 bidirectional Port G bit 8 GPIO; 5 V tolerant
94 VSS_9 power_in Ground supply 0 V
95 VDD_9 power_in Main digital supply voltage 2.0 to 3.6 V
96 PC6 bidirectional Port C bit 6 GPIO; I2S2 MCK, TIM8 CH1, SDIO data 6, TIM3 CH1; 5 V tolerant
97 PC7 bidirectional Port C bit 7 GPIO; I2S3 MCK, TIM8 CH2, SDIO data 7, TIM3 CH2; 5 V tolerant
98 PC8 bidirectional Port C bit 8 GPIO; TIM8 CH3, SDIO data 0, TIM3 CH3; 5 V tolerant
99 PC9 bidirectional Port C bit 9 GPIO; TIM8 CH4, SDIO data 1, TIM3 CH4; 5 V tolerant
100 PA8 bidirectional Port A bit 8 GPIO; USART1 CK, TIM1 CH1, MCO clock output; 5 V tolerant

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F103VCT6TR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f103vct6tr-etched.step / stm32f103vct6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f103vct6tr.step / stm32f103vct6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (143 pp, sha256 c61db5e362b62f2f, retrieved 2026-09-24, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF