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STM32F103V8T6

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STMicroelectronics Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F103V8T6

STMicroelectronics · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

STM32F103V8T6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant I/O, main function PE2, alternate function TRACECK (remap).
2 PE3 bidirectional 5 V-tolerant I/O, main function PE3, alternate function TRACED0 (remap).
3 PE4 bidirectional 5 V-tolerant I/O, main function PE4, alternate function TRACED1 (remap).
4 PE5 bidirectional 5 V-tolerant I/O, main function PE5, alternate function TRACED2 (remap).
5 PE6 bidirectional 5 V-tolerant I/O, main function PE6, alternate function TRACED3 (remap).
6 VBAT power_in Backup supply pin for RTC and backup registers.
7 PC13-TAMPER-RTC bidirectional I/O powered through the power switch (3 mA max sink): only one at a time as output, limited to 2 MHz with 30 pF max load, not a current source; function TAMPER-RTC.
8 PC14-OSC32_IN bidirectional I/O powered through the power switch (3 mA max sink), limited to 2 MHz with 30 pF max load; function OSC32_IN.
9 PC15-OSC32_OUT bidirectional I/O powered through the power switch (3 mA max sink), limited to 2 MHz with 30 pF max load; function OSC32_OUT.
10 VSS_5 power_in Ground supply pin.
11 VDD_5 power_in Digital supply pin, 2.0 to 3.6 V.
12 OSC_IN input Input of the 4-16 MHz HSE oscillator.
13 OSC_OUT output Output of the 4-16 MHz HSE oscillator.
14 NRST bidirectional Device reset input/output, active low.
15 PC0 bidirectional I/O with main function PC0 and ADC12_IN10 analog input.
16 PC1 bidirectional I/O with main function PC1 and ADC12_IN11 analog input.
17 PC2 bidirectional I/O with main function PC2 and ADC12_IN12 analog input.
18 PC3 bidirectional I/O with main function PC3 and ADC12_IN13 analog input.
19 VSSA power_in Analog ground supply pin.
20 VREF- power_in Negative reference voltage for the ADC.
21 VREF+ power_in Positive reference voltage for the ADC.
22 VDDA power_in Analog supply pin for ADC and analog blocks.
23 PA0-WKUP bidirectional I/O with WKUP, USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR functions.
24 PA1 bidirectional I/O with USART2_RTS, ADC12_IN1 and TIM2_CH2 functions.
25 PA2 bidirectional I/O with USART2_TX, ADC12_IN2 and TIM2_CH3 functions.
26 PA3 bidirectional I/O with USART2_RX, ADC12_IN3 and TIM2_CH4 functions.
27 VSS_4 power_in Ground supply pin.
28 VDD_4 power_in Digital supply pin, 2.0 to 3.6 V.
29 PA4 bidirectional I/O with SPI1_NSS, USART2_CK and ADC12_IN4 functions.
30 PA5 bidirectional I/O with SPI1_SCK and ADC12_IN5 functions.
31 PA6 bidirectional I/O with SPI1_MISO, ADC12_IN6, TIM3_CH1; remap TIM1_BKIN.
32 PA7 bidirectional I/O with SPI1_MOSI, ADC12_IN7, TIM3_CH2; remap TIM1_CH1N.
33 PC4 bidirectional I/O with main function PC4 and ADC12_IN14 analog input.
34 PC5 bidirectional I/O with main function PC5 and ADC12_IN15 analog input.
35 PB0 bidirectional I/O with ADC12_IN8, TIM3_CH3; remap TIM1_CH2N.
36 PB1 bidirectional I/O with ADC12_IN9, TIM3_CH4; remap TIM1_CH3N.
37 PB2 bidirectional 5 V-tolerant I/O, main function PB2/BOOT1.
38 PE7 bidirectional 5 V-tolerant I/O, remap TIM1_ETR.
39 PE8 bidirectional 5 V-tolerant I/O, remap TIM1_CH1N.
40 PE9 bidirectional 5 V-tolerant I/O, remap TIM1_CH1.
41 PE10 bidirectional 5 V-tolerant I/O, remap TIM1_CH2N.
42 PE11 bidirectional 5 V-tolerant I/O, remap TIM1_CH2.
43 PE12 bidirectional 5 V-tolerant I/O, remap TIM1_CH3N.
44 PE13 bidirectional 5 V-tolerant I/O, remap TIM1_CH3.
45 PE14 bidirectional 5 V-tolerant I/O, remap TIM1_CH4.
46 PE15 bidirectional 5 V-tolerant I/O, remap TIM1_BKIN.
47 PB10 bidirectional 5 V-tolerant I/O with I2C2_SCL, USART3_TX; remap TIM2_CH3.
48 PB11 bidirectional 5 V-tolerant I/O with I2C2_SDA, USART3_RX; remap TIM2_CH4.
49 VSS_1 power_in Ground supply pin.
50 VDD_1 power_in Digital supply pin, 2.0 to 3.6 V.
51 PB12 bidirectional 5 V-tolerant I/O with SPI2_NSS, I2C2_SMBAl, USART3_CK, TIM1_BKIN.
52 PB13 bidirectional 5 V-tolerant I/O with SPI2_SCK, USART3_CTS, TIM1_CH1N.
53 PB14 bidirectional 5 V-tolerant I/O with SPI2_MISO, USART3_RTS, TIM1_CH2N.
54 PB15 bidirectional 5 V-tolerant I/O with SPI2_MOSI, TIM1_CH3N.
55 PD8 bidirectional 5 V-tolerant I/O, remap USART3_TX.
56 PD9 bidirectional 5 V-tolerant I/O, remap USART3_RX.
57 PD10 bidirectional 5 V-tolerant I/O, remap USART3_CK.
58 PD11 bidirectional 5 V-tolerant I/O, remap USART3_CTS.
59 PD12 bidirectional 5 V-tolerant I/O, remap TIM4_CH1 / USART3_RTS.
60 PD13 bidirectional 5 V-tolerant I/O, remap TIM4_CH2.
61 PD14 bidirectional 5 V-tolerant I/O, remap TIM4_CH3.
62 PD15 bidirectional 5 V-tolerant I/O, remap TIM4_CH4.
63 PC6 bidirectional 5 V-tolerant I/O, remap TIM3_CH1.
64 PC7 bidirectional 5 V-tolerant I/O, remap TIM3_CH2.
65 PC8 bidirectional 5 V-tolerant I/O, remap TIM3_CH3.
66 PC9 bidirectional 5 V-tolerant I/O, remap TIM3_CH4.
67 PA8 bidirectional 5 V-tolerant I/O with USART1_CK, TIM1_CH1, MCO.
68 PA9 bidirectional 5 V-tolerant I/O with USART1_TX, TIM1_CH2.
69 PA10 bidirectional 5 V-tolerant I/O with USART1_RX, TIM1_CH3.
70 PA11 bidirectional 5 V-tolerant I/O with USART1_CTS, CANRX, USBDM, TIM1_CH4.
71 PA12 bidirectional 5 V-tolerant I/O with USART1_RTS, CANTX, USBDP, TIM1_ETR.
72 PA13 bidirectional 5 V-tolerant I/O, default JTMS/SWDIO debug function.
73 NC unconnected Not connected.
74 VSS_2 power_in Ground supply pin.
75 VDD_2 power_in Digital supply pin, 2.0 to 3.6 V.
76 PA14 bidirectional 5 V-tolerant I/O, default JTCK/SWCLK debug function.
77 PA15 bidirectional 5 V-tolerant I/O, default JTDI; remap TIM2_CH1_ETR / SPI1_NSS.
78 PC10 bidirectional 5 V-tolerant I/O, remap USART3_TX.
79 PC11 bidirectional 5 V-tolerant I/O, remap USART3_RX.
80 PC12 bidirectional 5 V-tolerant I/O, remap USART3_CK.
81 PD0 bidirectional 5 V-tolerant I/O, available by default on LQFP100; remap CANRX; output limited to 50 MHz.
82 PD1 bidirectional 5 V-tolerant I/O, available by default on LQFP100; remap CANTX; output limited to 50 MHz.
83 PD2 bidirectional 5 V-tolerant I/O, TIM3_ETR.
84 PD3 bidirectional 5 V-tolerant I/O, remap USART2_CTS.
85 PD4 bidirectional 5 V-tolerant I/O, remap USART2_RTS.
86 PD5 bidirectional 5 V-tolerant I/O, remap USART2_TX.
87 PD6 bidirectional 5 V-tolerant I/O, remap USART2_RX.
88 PD7 bidirectional 5 V-tolerant I/O, remap USART2_CK.
89 PB3 bidirectional 5 V-tolerant I/O, default JTDO; remap TIM2_CH2 / PB3 / TRACESWO / SPI1_SCK.
90 PB4 bidirectional 5 V-tolerant I/O, default JNTRST; remap TIM3_CH1 / PB4 / SPI1_MISO.
91 PB5 bidirectional I/O with I2C1_SMBAl; remap TIM3_CH2 / SPI1_MOSI.
92 PB6 bidirectional 5 V-tolerant I/O with I2C1_SCL, TIM4_CH1; remap USART1_TX.
93 PB7 bidirectional 5 V-tolerant I/O with I2C1_SDA, TIM4_CH2; remap USART1_RX.
94 BOOT0 input Boot mode selection input.
95 PB8 bidirectional 5 V-tolerant I/O with TIM4_CH3; remap I2C1_SCL / CANRX.
96 PB9 bidirectional 5 V-tolerant I/O with TIM4_CH4; remap I2C1_SDA / CANTX.
97 PE0 bidirectional 5 V-tolerant I/O, remap TIM4_ETR.
98 PE1 bidirectional 5 V-tolerant I/O, main function PE1.
99 VSS_3 power_in Ground supply pin.
100 VDD_3 power_in Digital supply pin, 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage VDD-VSS -0.3 4 V including VDDA and VDD 34
Input voltage on five volt tolerant pin VIN -0.3 5.5 V min printed VSS − 0.3 34
Variations between different VDD power pins /ΔVDDx/ 50 mV 34
Variations between all the different ground pins /VSSX − VSS/ 50 mV 34
Total current into VDD/VDDA power lines IVDD 150 mA source 35
Total current out of VSS ground lines IVSS 150 mA sink 35
Output current sunk or sourced by any I/O and control pin IIO 25 mA 35
Injected current on any pin IINJ(PIN) -5 5 mA NRST, OSC_IN or any other pin 35
Total injected current ΣIINJ(PIN) -25 25 mA sum of all I/O and control pins 35
Storage temperature range TSTG -65 150 °C 35
Maximum junction temperature TJ 150 °C 35
Internal AHB clock frequency fHCLK 0 72 MHz 35
Internal APB1 clock frequency fPCLK1 0 36 MHz 35
Internal APB2 clock frequency fPCLK2 0 72 MHz 35
Standard operating voltage VDD 2 3.6 V 35
Analog operating voltage (ADC not used) VDDA 2 3.6 V Must be the same potential as VDD 35
Analog operating voltage (ADC used) VDDA 2.4 3.6 V Must be the same potential as VDD 35
Backup operating voltage VBAT 1.8 3.6 V 35
Power dissipation LQFP100 PD 434 mW TA = 85 °C for suffix 6 36
Ambient temperature, 6 suffix, maximum power dissipation TA -40 85 °C 6 suffix version 36
Junction temperature range, 6 suffix TJ -40 105 °C 6 suffix version 36
VDD fall time rate tVDD 20 µs/V 36
VDD rise time rate tVDD 0 µs/V 36
Power on/power down reset threshold, falling edge VPOR/PDR 1.8 1.88 1.96 V Falling edge 37
Power on/power down reset threshold, rising edge VPOR/PDR 1.84 1.92 2 V Rising edge 37
PVD level selection, rising edge VPVD 2.1 2.18 2.26 V PLS[2:0]=000 (rising edge) 37
PVD level selection, falling edge VPVD 2 2.08 2.16 V PLS[2:0]=000 (falling edge) 37
PVD level selection, rising edge VPVD 2.76 2.88 3 V PLS[2:0]=111 (rising edge) 37
PVD level selection, falling edge VPVD 2.66 2.78 2.9 V PLS[2:0]=111 (falling edge) 37
Reset temporization TRSTTEMPO 1 2.5 4.5 ms 37
Internal reference voltage VREFINT 1.16 1.2 1.24 V -40 °C < TA < +85 °C 38
ADC sampling time when reading internal reference voltage TS_vrefint 5.1 17.1 µs 38
Supply current in Run mode, flash, all peripherals enabled IDD 50 mA External clock, 72 MHz, TA = 85 °C 39
Supply current in Run mode, flash, all peripherals disabled IDD 32.8 mA External clock, 72 MHz, TA = 85 °C 39
Supply current in Sleep mode, all peripherals enabled IDD 30 mA External clock, 72 MHz, TA = 85 °C 41
Supply current in Stop mode, regulator in Run mode IDD 24 200 µA TA = 85 °C; typ VDD/VBAT = 3.3 V 42
Supply current in Stop mode, regulator in Low Power mode IDD 14 180 µA TA = 85 °C; typ VDD/VBAT = 3.3 V 42
Supply current in Standby mode, LSI, IWDG, LSE and RTC off IDD 2 4 µA TA = 85 °C; typ VDD/VBAT = 3.3 V 42
Backup domain supply current IDD_VBAT 1.4 1.9 µA Low-speed oscillator and RTC ON, TA = 85 °C; typ VDD/VBAT = 3.3 V 42
User external clock source frequency (HSE) fHSE_ext 8 25 MHz 47
HSE oscillator frequency fOSC_IN 4 8 16 MHz 49
HSI accuracy ACCHSI -1.5 1 2.2 % TA = -10 to 85 °C 51
HSI accuracy ACCHSI -1.1 1 1.8 % TA = 25 °C 51
LSI oscillator frequency fLSI 30 40 60 kHz VDD = 3 V, TA = -40 to 105 °C 51
PLL input clock fPLL_IN 1 8 25 MHz 52
PLL multiplier output clock fPLL_OUT 16 72 MHz 52
16-bit programming time tprog 40 52.5 70 µs TA -40 to +105 °C 52
Flash endurance NEND 10 kcycles TA = -40 to +85 °C (6 suffix versions) 53
Input low level voltage TTL ports VIL -0.5 0.8 V TTL ports 56
Standard IO input high level voltage TTL VIH 2 V TTL ports 56
IO FT input high level voltage VIH 2 5.5 V TTL ports 56
Input leakage current, standard I/Os Ilkg 1 µA VSS ≤ VIN ≤ VDD 56
Weak pull-up equivalent resistor RPU 30 40 50 kΩ VIN = VSS 56
Output low level voltage, 8 mA VOL 0.4 V TTL port, IIO = +8 mA, 2.7 V < VDD < 3.6 V 57
Output low level voltage, 20 mA VOL 1.3 V IIO = +20 mA, 2.7 V < VDD < 3.6 V 57
NRST weak pull-up equivalent resistor RPU 30 40 50 kΩ VIN = VSS 59
USB operating voltage VDD 3 3.6 V 66
I/O pin capacitance CIO 5 pF 56

CAD (KiCad official)

  • Symbol: STM32F103V8T6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f103v8t6-etched.step / stm32f103v8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f103v8t6.step / stm32f103v8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (91 pp, sha256 1d2409eb5c66ba92, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF