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STM32F103TBU7

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UQFN-36-EP(6x6). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F103TBU7

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UQFN-36-EP(6x6)

STM32F103TBU7 from STMicroelectronics, in a UQFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD_3 power_in Digital supply pin for the I/O ring and core; the application supply and I/Os operate from 2.0 to 3.6 V.
2 OSC_IN input High-speed external oscillator input (4-16 MHz crystal) that is the default function after reset; PD0 can be selected by software remap, and in output mode PD0 is limited to 50 MHz.
3 OSC_OUT output High-speed external oscillator output (4-16 MHz crystal) that is the default function after reset; PD1 can be selected by software remap, and in output mode PD1 is limited to 50 MHz.
4 NRST bidirectional Reset pin; its electrical characteristics are specified in the NRST pin characteristics section (5.3.14).
5 VSSA power_in Analog ground reference for the ADC and analog circuitry; all voltages are referenced to VSS.
6 VDDA power_in Analog supply for the ADC and temperature sensor; the temperature sensor conversion range is 2 V < VDDA < 3.6 V.
7 PA0-WKUP bidirectional GPIO PA0 (not marked 5 V tolerant) with WKUP wake-up, USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR alternate functions.
8 PA1 bidirectional GPIO PA1 (not marked 5 V tolerant) with USART2_RTS, ADC12_IN1 and TIM2_CH2 alternate functions.
9 PA2 bidirectional GPIO PA2 (not marked 5 V tolerant) with USART2_TX, ADC12_IN2 and TIM2_CH3 alternate functions.
10 PA3 bidirectional GPIO PA3 (not marked 5 V tolerant) with USART2_RX, ADC12_IN3 and TIM2_CH4 alternate functions.
11 PA4 bidirectional GPIO PA4 (not marked 5 V tolerant) with SPI1_NSS, USART2_CK and ADC12_IN4 alternate functions.
12 PA5 bidirectional GPIO PA5 (not marked 5 V tolerant) with SPI1_SCK and ADC12_IN5 alternate functions.
13 PA6 bidirectional GPIO PA6 (not marked 5 V tolerant) with SPI1_MISO, ADC12_IN6, TIM3_CH1 and remapped TIM1_BKIN alternate functions.
14 PA7 bidirectional GPIO PA7 (not marked 5 V tolerant) with SPI1_MOSI, ADC12_IN7, TIM3_CH2 and remapped TIM1_CH1N alternate functions.
15 PB0 bidirectional GPIO PB0 (not marked 5 V tolerant) with ADC12_IN8, TIM3_CH3 and remapped TIM1_CH2N alternate functions.
16 PB1 bidirectional GPIO PB1 (not marked 5 V tolerant) with ADC12_IN9, TIM3_CH4 and remapped TIM1_CH3N alternate functions.
17 PB2/BOOT1 bidirectional 5 V tolerant GPIO PB2 that also serves as the BOOT1 boot-mode configuration pin.
18 VSS_1 power_in Digital ground pin for the I/O ring and core.
19 VDD_1 power_in Digital supply pin for the I/O ring and core; the application supply and I/Os operate from 2.0 to 3.6 V.
20 PA8 bidirectional 5 V tolerant GPIO PA8 with USART1_CK, TIM1_CH1 and MCO alternate functions.
21 PA9 bidirectional 5 V tolerant GPIO PA9 with USART1_TX and TIM1_CH2 alternate functions.
22 PA10 bidirectional 5 V tolerant GPIO PA10 with USART1_RX and TIM1_CH3 alternate functions.
23 PA11 bidirectional 5 V tolerant GPIO PA11 with USART1_CTS, CANRX, USBDM and TIM1_CH4 alternate functions.
24 PA12 bidirectional 5 V tolerant GPIO PA12 with USART1_RTS, CANTX, USBDP and TIM1_ETR alternate functions.
25 PA13 bidirectional 5 V tolerant GPIO PA13; its default function is JTMS/SWDIO (serial wire debug data).
26 VSS_2 power_in Digital ground pin for the I/O ring and core.
27 VDD_2 power_in Digital supply pin for the I/O ring and core; the application supply and I/Os operate from 2.0 to 3.6 V.
28 PA14 bidirectional 5 V tolerant GPIO PA14; its default function is JTCK/SWCLK (serial wire debug clock).
29 PA15 bidirectional 5 V tolerant GPIO PA15; its default function is JTDI, with TIM2_CH1_ETR and SPI1_NSS alternate functions.
30 PB3 bidirectional 5 V tolerant GPIO PB3; its default function is JTDO, with TIM2_CH2, TRACESWO and remapped SPI1_SCK alternate functions.
31 PB4 bidirectional 5 V tolerant GPIO PB4; its default function is JNTRST, with TIM3_CH1 and remapped SPI1_MISO alternate functions.
32 PB5 bidirectional GPIO PB5 (not marked 5 V tolerant) with I2C1_SMBAL, TIM3_CH2 and remapped SPI1_MOSI alternate functions.
33 PB6 bidirectional 5 V tolerant GPIO PB6 with I2C1_SCL, TIM4_CH1 and USART1_TX alternate functions.
34 PB7 bidirectional 5 V tolerant GPIO PB7 with I2C1_SDA, TIM4_CH2 and USART1_RX alternate functions.
35 BOOT0 input Boot mode selection input (BOOT0); the boot mode behaviour is described in the Boot modes section of the datasheet.
36 VSS_3 power_in Digital ground pin for the I/O ring and core.
37 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UQFN-36-EP(6x6)
Category Embedded Processors & Controllers
Pins 37

CAD (KiCad official)

  • Symbol: STM32F103TBU7
  • Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • 3D model: UQFN-36-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: stm32f103tbu7-etched.step / stm32f103tbu7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f103tbu7.step / stm32f103tbu7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (117 pp, sha256 4741c03c5793745c, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF