component
STM32F103RCT7
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F103RCT7
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32F103RCT7 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Battery backup supply for RTC, external 32 kHz oscillator, and backup registers; 1.8 to 3.6 V when VDD is not present. |
| 2 | PC13-TAMPER-RTC | bidirectional | GPIO PC13 supplied through power switch; limited to ≤3 mA, ≤2 MHz, 30 pF max load; alternate TAMPER-RTC function. |
| 3 | PC14-OSC32_IN | bidirectional | GPIO PC14 supplied through power switch; limited to ≤3 mA, ≤2 MHz, 30 pF max load; alternate LSE 32.768 kHz oscillator input. |
| 4 | PC15-OSC32_OUT | bidirectional | GPIO PC15 supplied through power switch; limited to ≤3 mA, ≤2 MHz, 30 pF max load; alternate LSE 32.768 kHz oscillator output. |
| 5 | OSC_IN | input | HSE crystal/resonator input for 4-16 MHz oscillator or 1-25 MHz external clock; PD0 (CAN_RX/FSMC_D2) software-remappable onto this pin. |
| 6 | OSC_OUT | output | HSE crystal/resonator feedback output; PD1 (CAN_TX/FSMC_D3) software-remappable onto this pin. |
| 7 | NRST | bidirectional | Active-low system reset with Schmitt trigger input and permanent 30-50 kΩ pull-up; pulses <100 ns filtered, ≥300 ns guaranteed to trigger reset. |
| 8 | PC0 | bidirectional | GPIO PC0; alternate ADC123_IN10 (analog input channel 10, shared ADC1/2/3, 0 V to VREF+ range). |
| 9 | PC1 | bidirectional | GPIO PC1; alternate ADC123_IN11 (analog input channel 11, shared ADC1/2/3). |
| 10 | PC2 | bidirectional | GPIO PC2; alternate ADC123_IN12 (analog input channel 12, shared ADC1/2/3). |
| 11 | PC3 | bidirectional | GPIO PC3; alternate ADC123_IN13 (analog input channel 13, shared ADC1/2/3). |
| 12 | VSSA | power_in | Analog ground reference for ADC, DAC, reset block, RC oscillators, and PLL; must be connected to VSS. |
| 13 | VDDA | power_in | Analog power supply for ADC, DAC, PLL, and RC oscillators; 2.0-3.6 V (minimum 2.4 V when ADC or DAC is used). |
| 14 | PA0-WKUP | bidirectional | GPIO PA0; Standby-mode wakeup pin; alternate USART2_CTS, ADC123_IN0, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR. |
| 15 | PA1 | bidirectional | GPIO PA1; alternate USART2_RTS, ADC123_IN1, TIM5_CH2, TIM2_CH2. |
| 16 | PA2 | bidirectional | GPIO PA2; alternate USART2_TX, TIM5_CH3, ADC123_IN2, TIM2_CH3. |
| 17 | PA3 | bidirectional | GPIO PA3; alternate USART2_RX, TIM5_CH4, ADC123_IN3, TIM2_CH4. |
| 18 | VSS_4 | power_in | Digital ground supply pin (VSS_4); must be connected to system ground. |
| 19 | VDD_4 | power_in | Main digital I/O and internal regulator supply (VDD_4); 2.0 to 3.6 V. |
| 20 | PA4 | bidirectional | GPIO PA4; alternate SPI1_NSS, USART2_CK, DAC_OUT1, ADC12_IN4. |
| 21 | PA5 | bidirectional | GPIO PA5; alternate SPI1_SCK, DAC_OUT2, ADC12_IN5. |
| 22 | PA6 | bidirectional | GPIO PA6; alternate SPI1_MISO, TIM8_BKIN, ADC12_IN6; remap TIM3_CH1, TIM1_BKIN. |
| 23 | PA7 | bidirectional | GPIO PA7; alternate SPI1_MOSI, TIM8_CH1N, ADC12_IN7; remap TIM3_CH2, TIM1_CH1N. |
| 24 | PC4 | bidirectional | GPIO PC4; alternate ADC12_IN14 (analog input channel 14, shared ADC1/2). |
| 25 | PC5 | bidirectional | GPIO PC5; alternate ADC12_IN15 (analog input channel 15, shared ADC1/2). |
| 26 | PB0 | bidirectional | GPIO PB0; alternate ADC12_IN8, TIM3_CH3, TIM8_CH2N; remap TIM1_CH2N. |
| 27 | PB1 | bidirectional | GPIO PB1; alternate ADC12_IN9, TIM3_CH4, TIM8_CH3N; remap TIM1_CH3N. |
| 28 | PB2 | bidirectional | 5 V-tolerant GPIO PB2; dual-function as BOOT1 boot configuration pin sampled at reset. |
| 29 | PB10 | bidirectional | 5 V-tolerant GPIO PB10; alternate I2C2_SCL, USART3_TX; remap TIM2_CH3. |
| 30 | PB11 | bidirectional | 5 V-tolerant GPIO PB11; alternate I2C2_SDA, USART3_RX; remap TIM2_CH4. |
| 31 | VSS_1 | power_in | Digital ground supply pin (VSS_1); must be connected to system ground. |
| 32 | VDD_1 | power_in | Main digital I/O and internal regulator supply (VDD_1); 2.0 to 3.6 V. |
| 33 | PB12 | bidirectional | 5 V-tolerant GPIO PB12; alternate SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN. |
| 34 | PB13 | bidirectional | 5 V-tolerant GPIO PB13; alternate SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N. |
| 35 | PB14 | bidirectional | 5 V-tolerant GPIO PB14; alternate SPI2_MISO, TIM1_CH2N; remap USART3_RTS. |
| 36 | PB15 | bidirectional | 5 V-tolerant GPIO PB15; alternate SPI2_MOSI/I2S2_SD; remap TIM1_CH3N. |
| 37 | PC6 | bidirectional | 5 V-tolerant GPIO PC6; alternate I2S2_MCK, TIM8_CH1, SDIO_D6; remap TIM3_CH1. |
| 38 | PC7 | bidirectional | 5 V-tolerant GPIO PC7; alternate I2S3_MCK, TIM8_CH2, SDIO_D7; remap TIM3_CH2. |
| 39 | PC8 | bidirectional | 5 V-tolerant GPIO PC8; alternate TIM8_CH3, SDIO_D0; remap TIM3_CH3. |
| 40 | PC9 | bidirectional | 5 V-tolerant GPIO PC9; alternate TIM8_CH4, SDIO_D1; remap TIM3_CH4. |
| 41 | PA8 | bidirectional | 5 V-tolerant GPIO PA8; alternate USART1_CK, TIM1_CH1, MCO (microcontroller clock output). |
| 42 | PA9 | bidirectional | 5 V-tolerant GPIO PA9; alternate USART1_TX (up to 4.5 Mbit/s), TIM1_CH2. |
| 43 | PA10 | bidirectional | 5 V-tolerant GPIO PA10; alternate USART1_RX, TIM1_CH3. |
| 44 | PA11 | bidirectional | 5 V-tolerant GPIO PA11; alternate USART1_CTS, USB_DM (USB full-speed D−), CAN_RX, TIM1_CH4. |
| 45 | PA12 | bidirectional | 5 V-tolerant GPIO PA12; alternate USART1_RTS, USB_DP (USB full-speed D+), CAN_TX, TIM1_ETR. |
| 46 | PA13 | bidirectional | 5 V-tolerant GPIO PA13; default JTMS-SWDIO (JTAG TMS / SWD bidirectional data); remappable to PA13 GPIO. |
| 47 | VSS_2 | power_in | Digital ground supply pin (VSS_2); must be connected to system ground. |
| 48 | VDD_2 | power_in | Main digital I/O and internal regulator supply (VDD_2); 2.0 to 3.6 V. |
| 49 | PA14 | bidirectional | 5 V-tolerant GPIO PA14; default JTCK-SWCLK (JTAG TCK / SWD clock); remappable to PA14 GPIO. |
| 50 | PA15 | bidirectional | 5 V-tolerant GPIO PA15; default JTDI; remap SPI3_NSS/I2S3_WS, TIM2_CH1_ETR, SPI1_NSS. |
| 51 | PC10 | bidirectional | 5 V-tolerant GPIO PC10; alternate UART4_TX, SDIO_D2; remap USART3_TX. |
| 52 | PC11 | bidirectional | 5 V-tolerant GPIO PC11; alternate UART4_RX, SDIO_D3; remap USART3_RX. |
| 53 | PC12 | bidirectional | 5 V-tolerant GPIO PC12; alternate UART5_TX, SDIO_CK; remap USART3_CK. |
| 54 | PD2 | bidirectional | 5 V-tolerant GPIO PD2; alternate TIM3_ETR, UART5_RX, SDIO_CMD. |
| 55 | PB3 | bidirectional | 5 V-tolerant GPIO PB3; default JTDO; remap SPI3_SCK/I2S3_CK, TIM2_CH2, SPI1_SCK, TRACESWO. |
| 56 | PB4 | bidirectional | 5 V-tolerant GPIO PB4; default NJTRST (JTAG reset); remap SPI3_MISO, TIM3_CH1, SPI1_MISO. |
| 57 | PB5 | bidirectional | GPIO PB5 (not 5 V-tolerant); alternate I2C1_SMBA, SPI3_MOSI/I2S3_SD; remap TIM3_CH2, SPI1_MOSI. |
| 58 | PB6 | bidirectional | 5 V-tolerant GPIO PB6; alternate I2C1_SCL, TIM4_CH1; remap USART1_TX. |
| 59 | PB7 | bidirectional | 5 V-tolerant GPIO PB7; alternate I2C1_SDA, FSMC_NADV, TIM4_CH2; remap USART1_RX. |
| 60 | BOOT0 | input | Boot mode select pin sampled at reset; high combined with BOOT1 state selects system-memory or SRAM boot; pull low for normal Flash boot. |
| 61 | PB8 | bidirectional | 5 V-tolerant GPIO PB8; alternate TIM4_CH3, SDIO_D4; remap I2C1_SCL, CAN_RX. |
| 62 | PB9 | bidirectional | 5 V-tolerant GPIO PB9; alternate TIM4_CH4, SDIO_D5; remap I2C1_SDA, CAN_TX. |
| 63 | VSS_3 | power_in | Digital ground supply pin (VSS_3); must be connected to system ground. |
| 64 | VDD_3 | power_in | Main digital I/O and internal regulator supply (VDD_3); 2.0 to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32F103RCT7 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32f103rct7-etched.step/stm32f103rct7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f103rct7.step/stm32f103rct7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (143 pp, sha256
c61db5e362b62f2f, retrieved 2026-09-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).