# STM32F103RBT6TR

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F103RBT6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup supply for the RTC and backup registers. |
| 2 | PC13-TAMPER-RTC | bidirectional | GPIO PC13 with TAMPER-RTC function; supplied through the power switch, so output mode is limited to 2 MHz with 30 pF max load (3 mA sink limit) and it must not source current. |
| 3 | PC14-OSC32_IN | bidirectional | GPIO PC14 or OSC32_IN (LSE oscillator input); supplied through the power switch, output limited to 2 MHz with 30 pF max load. |
| 4 | PC15-OSC32_OUT | bidirectional | GPIO PC15 or OSC32_OUT (LSE oscillator output); supplied through the power switch, output limited to 2 MHz with 30 pF max load. |
| 5 | OSC_IN | input | Main oscillator input (4-16 MHz HSE) after reset; can be remapped as PD0. |
| 6 | OSC_OUT | output | Main oscillator output (4-16 MHz HSE) after reset; can be remapped as PD1. |
| 7 | NRST | bidirectional | Device reset input/output, active low. |
| 8 | PC0 | bidirectional | General-purpose I/O PC0 with alternate function ADC12_IN10. |
| 9 | PC1 | bidirectional | General-purpose I/O PC1 with alternate function ADC12_IN11. |
| 10 | PC2 | bidirectional | General-purpose I/O PC2 with alternate function ADC12_IN12. |
| 11 | PC3 | bidirectional | General-purpose I/O PC3 with alternate function ADC12_IN13. |
| 12 | VSSA | power_in | Analog ground for the ADC and analog circuitry. |
| 13 | VDDA | power_in | Analog power supply. |
| 14 | PA0-WKUP | bidirectional | GPIO PA0 with WKUP, USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR alternate functions. |
| 15 | PA1 | bidirectional | GPIO PA1 with USART2_RTS, ADC12_IN1 and TIM2_CH2 alternate functions. |
| 16 | PA2 | bidirectional | GPIO PA2 with USART2_TX, ADC12_IN2 and TIM2_CH3 alternate functions. |
| 17 | PA3 | bidirectional | GPIO PA3 with USART2_RX, ADC12_IN3 and TIM2_CH4 alternate functions. |
| 18 | VSS_4 | power_in | Digital ground. |
| 19 | VDD_4 | power_in | Digital power supply. |
| 20 | PA4 | bidirectional | GPIO PA4 with SPI1_NSS, USART2_CK and ADC12_IN4 alternate functions. |
| 21 | PA5 | bidirectional | GPIO PA5 with SPI1_SCK and ADC12_IN5 alternate functions. |
| 22 | PA6 | bidirectional | GPIO PA6 with SPI1_MISO, ADC12_IN6 and TIM3_CH1 alternate functions; TIM1_BKIN on remap. |
| 23 | PA7 | bidirectional | GPIO PA7 with SPI1_MOSI, ADC12_IN7 and TIM3_CH2 alternate functions; TIM1_CH1N on remap. |
| 24 | PC4 | bidirectional | General-purpose I/O PC4 with alternate function ADC12_IN14. |
| 25 | PC5 | bidirectional | General-purpose I/O PC5 with alternate function ADC12_IN15. |
| 26 | PB0 | bidirectional | GPIO PB0 with ADC12_IN8 and TIM3_CH3 alternate functions; TIM1_CH2N on remap. |
| 27 | PB1 | bidirectional | GPIO PB1 with ADC12_IN9 and TIM3_CH4 alternate functions; TIM1_CH3N on remap. |
| 28 | PB2 | bidirectional | 5 V tolerant GPIO PB2, also BOOT1 boot-mode select after reset. |
| 29 | PB10 | bidirectional | 5 V tolerant GPIO PB10 with I2C2_SCL and USART3_TX; TIM2_CH3 on remap. |
| 30 | PB11 | bidirectional | 5 V tolerant GPIO PB11 with I2C2_SDA and USART3_RX; TIM2_CH4 on remap. |
| 31 | VSS_1 | power_in | Digital ground. |
| 32 | VDD_1 | power_in | Digital power supply. |
| 33 | PB12 | bidirectional | 5 V tolerant GPIO PB12 with SPI2_NSS, I2C2_SMBAl, USART3_CK and TIM1_BKIN. |
| 34 | PB13 | bidirectional | 5 V tolerant GPIO PB13 with SPI2_SCK, USART3_CTS and TIM1_CH1N. |
| 35 | PB14 | bidirectional | 5 V tolerant GPIO PB14 with SPI2_MISO, USART3_RTS and TIM1_CH2N. |
| 36 | PB15 | bidirectional | 5 V tolerant GPIO PB15 with SPI2_MOSI and TIM1_CH3N. |
| 37 | PC6 | bidirectional | 5 V tolerant GPIO PC6; TIM3_CH1 on remap. |
| 38 | PC7 | bidirectional | 5 V tolerant GPIO PC7; TIM3_CH2 on remap. |
| 39 | PC8 | bidirectional | 5 V tolerant GPIO PC8; TIM3_CH3 on remap. |
| 40 | PC9 | bidirectional | 5 V tolerant GPIO PC9; TIM3_CH4 on remap. |
| 41 | PA8 | bidirectional | 5 V tolerant GPIO PA8 with USART1_CK, TIM1_CH1 and MCO. |
| 42 | PA9 | bidirectional | 5 V tolerant GPIO PA9 with USART1_TX and TIM1_CH2. |
| 43 | PA10 | bidirectional | 5 V tolerant GPIO PA10 with USART1_RX and TIM1_CH3. |
| 44 | PA11 | bidirectional | 5 V tolerant GPIO PA11 with USART1_CTS, CANRX, USBDM and TIM1_CH4. |
| 45 | PA12 | bidirectional | 5 V tolerant GPIO PA12 with USART1_RTS, CANTX, USBDP; TIM1_ETR on remap. |
| 46 | PA13 | bidirectional | 5 V tolerant pin, JTMS/SWDIO after reset; PA13 on remap. |
| 47 | VSS_2 | power_in | Digital ground. |
| 48 | VDD_2 | power_in | Digital power supply. |
| 49 | PA14 | bidirectional | 5 V tolerant pin, JTCK/SWCLK after reset; PA14 on remap. |
| 50 | PA15 | bidirectional | 5 V tolerant pin, JTDI after reset; TIM2_CH1_ETR, PA15 and SPI1_NSS on remap. |
| 51 | PC10 | bidirectional | 5 V tolerant GPIO PC10; USART3_TX on remap. |
| 52 | PC11 | bidirectional | 5 V tolerant GPIO PC11; USART3_RX on remap. |
| 53 | PC12 | bidirectional | 5 V tolerant GPIO PC12; USART3_CK on remap. |
| 54 | PD2 | bidirectional | 5 V tolerant GPIO PD2 with TIM3_ETR alternate function. |
| 55 | PB3 | bidirectional | 5 V tolerant pin, JTDO after reset; TIM2_CH2, PB3, TRACESWO and SPI1_SCK on remap. |
| 56 | PB4 | bidirectional | 5 V tolerant pin, JNTRST after reset; TIM3_CH1, PB4 and SPI1_MISO on remap. |
| 57 | PB5 | bidirectional | GPIO PB5 with I2C1_SMBAl; TIM3_CH2 and SPI1_MOSI on remap (not marked 5 V tolerant in the table). |
| 58 | PB6 | bidirectional | 5 V tolerant GPIO PB6 with I2C1_SCL and TIM4_CH1; USART1_TX on remap. |
| 59 | PB7 | bidirectional | 5 V tolerant GPIO PB7 with I2C1_SDA and TIM4_CH2; USART1_RX on remap. |
| 60 | BOOT0 | input | Boot mode selection input. |
| 61 | PB8 | bidirectional | 5 V tolerant GPIO PB8 with TIM4_CH3; I2C1_SCL and CANRX on remap. |
| 62 | PB9 | bidirectional | 5 V tolerant GPIO PB9 with TIM4_CH4; I2C1_SDA and CANTX on remap. |
| 63 | VSS_3 | power_in | Digital ground. |
| 64 | VDD_3 | power_in | Digital power supply. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## CAD (KiCad official)

- Symbol: `STM32F103RBT6TR`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `stm32f103rbt6tr-etched.step` / `stm32f103rbt6tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32f103rbt6tr.step` / `stm32f103rbt6tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234915938725888) (116 pp, sha256 `0596dd57693c93d2`, retrieved 2026-10-01, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32f103rbt6tr-datasheet.pdf)