component

STM32F103R8T7

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f103r8t7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers stm32f103r8t7: viewers · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Initial commit: component/stm32f103r8t7 · Ray 2d ago
stm32f103r8t7-etched.glb stm32f103r8t7: factory component page (tier=lcsc) · Ray 2d ago
stm32f103r8t7-etched.step stm32f103r8t7: factory component page (tier=lcsc) · Ray 2d ago
stm32f103r8t7-hero.glb Publish 0.1.0 · Ray 2d ago
stm32f103r8t7-hero.overlay.json Publish 0.1.0 · Ray 2d ago
stm32f103r8t7.glb Publish 0.1.0 · Ray 2d ago
stm32f103r8t7.kicad_mod Publish 0.1.0 · Ray 2d ago
stm32f103r8t7.kicad_sym Publish 0.1.0 · Ray 2d ago
stm32f103r8t7.lbr Publish 0.1.0 · Ray 2d ago
stm32f103r8t7.step Publish 0.1.0 · Ray 2d ago

STM32F103R8T7

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F103R8T7 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup supply pin for the RTC and backup registers.
2 PC13-TAMPER-RTC bidirectional GPIO PC13 (after backup domain power-up) with TAMPER-RTC alternate function; supplied through the power switch, so output mode is limited to 2 MHz with 30 pF max load and no current-source use (3 mA).
3 PC14-OSC32_IN bidirectional GPIO PC14 (after backup domain power-up) or OSC32_IN 32 kHz oscillator input; output mode limited to 2 MHz with 30 pF max load.
4 PC15-OSC32_OUT bidirectional GPIO PC15 (after backup domain power-up) or OSC32_OUT 32 kHz oscillator output; output mode limited to 2 MHz with 30 pF max load.
5 OSC_IN input Main function after reset is OSC_IN (4-16 MHz oscillator input); can be remapped to PD0.
6 OSC_OUT output Main function after reset is OSC_OUT (4-16 MHz oscillator output); can be remapped to PD1.
7 NRST bidirectional Device reset input/output, main function NRST after reset.
8 PC0 bidirectional General-purpose I/O PC0 (not 5 V tolerant) with ADC12_IN10 alternate function.
9 PC1 bidirectional General-purpose I/O PC1 (not 5 V tolerant) with ADC12_IN11 alternate function.
10 PC2 bidirectional General-purpose I/O PC2 (not 5 V tolerant) with ADC12_IN12 alternate function.
11 PC3 bidirectional General-purpose I/O PC3 (not 5 V tolerant) with ADC12_IN13 alternate function.
12 VSSA power_in Analog ground supply.
13 VDDA power_in Analog supply voltage.
14 PA0-WKUP bidirectional GPIO PA0 with WKUP, USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR alternate functions.
15 PA1 bidirectional GPIO PA1 with USART2_RTS, ADC12_IN1 and TIM2_CH2 alternate functions.
16 PA2 bidirectional GPIO PA2 with USART2_TX, ADC12_IN2 and TIM2_CH3 alternate functions.
17 PA3 bidirectional GPIO PA3 with USART2_RX, ADC12_IN3 and TIM2_CH4 alternate functions.
18 VSS_4 power_in Digital ground supply.
19 VDD_4 power_in Digital supply voltage (2.0 to 3.6 V application supply).
20 PA4 bidirectional GPIO PA4 with SPI1_NSS, USART2_CK and ADC12_IN4 alternate functions.
21 PA5 bidirectional GPIO PA5 with SPI1_SCK and ADC12_IN5 alternate functions.
22 PA6 bidirectional GPIO PA6 with SPI1_MISO, ADC12_IN6, TIM3_CH1; remap TIM1_BKIN.
23 PA7 bidirectional GPIO PA7 with SPI1_MOSI, ADC12_IN7, TIM3_CH2; remap TIM1_CH1N.
24 PC4 bidirectional General-purpose I/O PC4 (not 5 V tolerant) with ADC12_IN14 alternate function.
25 PC5 bidirectional General-purpose I/O PC5 (not 5 V tolerant) with ADC12_IN15 alternate function.
26 PB0 bidirectional GPIO PB0 with ADC12_IN8, TIM3_CH3; remap TIM1_CH2N.
27 PB1 bidirectional GPIO PB1 with ADC12_IN9, TIM3_CH4; remap TIM1_CH3N.
28 PB2/BOOT1 bidirectional 5 V tolerant GPIO PB2 that also serves as BOOT1 boot mode selection.
29 PB10 bidirectional 5 V tolerant GPIO PB10 with I2C2_SCL, USART3_TX; remap TIM2_CH3.
30 PB11 bidirectional 5 V tolerant GPIO PB11 with I2C2_SDA, USART3_RX; remap TIM2_CH4.
31 VSS_1 power_in Digital ground supply.
32 VDD_1 power_in Digital supply voltage (2.0 to 3.6 V application supply).
33 PB12 bidirectional 5 V tolerant GPIO PB12 with SPI2_NSS, I2C2_SMBAl, USART3_CK, TIM1_BKIN.
34 PB13 bidirectional 5 V tolerant GPIO PB13 with SPI2_SCK, USART3_CTS, TIM1_CH1N.
35 PB14 bidirectional 5 V tolerant GPIO PB14 with SPI2_MISO, USART3_RTS, TIM1_CH2N.
36 PB15 bidirectional 5 V tolerant GPIO PB15 with SPI2_MOSI and TIM1_CH3N.
37 PC6 bidirectional 5 V tolerant GPIO PC6; remap TIM3_CH1.
38 PC7 bidirectional 5 V tolerant GPIO PC7; remap TIM3_CH2.
39 PC8 bidirectional 5 V tolerant GPIO PC8; remap TIM3_CH3.
40 PC9 bidirectional 5 V tolerant GPIO PC9; remap TIM3_CH4.
41 PA8 bidirectional 5 V tolerant GPIO PA8 with USART1_CK, TIM1_CH1 and MCO.
42 PA9 bidirectional 5 V tolerant GPIO PA9 with USART1_TX and TIM1_CH2.
43 PA10 bidirectional 5 V tolerant GPIO PA10 with USART1_RX and TIM1_CH3.
44 PA11 bidirectional 5 V tolerant GPIO PA11 with USART1_CTS, CANRX, USBDM, TIM1_CH4.
45 PA12 bidirectional 5 V tolerant GPIO PA12 with USART1_RTS, CANTX, USBDP; remap TIM1_ETR.
46 PA13 bidirectional 5 V tolerant pin, JTMS/SWDIO after reset; PA13 via remap.
47 VSS_2 power_in Digital ground supply.
48 VDD_2 power_in Digital supply voltage (2.0 to 3.6 V application supply).
49 PA14 bidirectional 5 V tolerant pin, JTCK/SWCLK after reset; PA14 via remap.
50 PA15 bidirectional 5 V tolerant pin, JTDI after reset; remap TIM2_CH1_ETR, PA15, SPI1_NSS.
51 PC10 bidirectional 5 V tolerant GPIO PC10; remap USART3_TX.
52 PC11 bidirectional 5 V tolerant GPIO PC11; remap USART3_RX.
53 PC12 bidirectional 5 V tolerant GPIO PC12; remap USART3_CK.
54 PD2 bidirectional 5 V tolerant GPIO PD2 with TIM3_ETR alternate function.
55 PB3 bidirectional 5 V tolerant pin, JTDO after reset; remap TIM2_CH2, PB3, TRACESWO, SPI1_SCK.
56 PB4 bidirectional 5 V tolerant pin, JNTRST after reset; remap TIM3_CH1, PB4, SPI1_MISO.
57 PB5 bidirectional GPIO PB5 (not 5 V tolerant) with I2C1_SMBAl; remap TIM3_CH2, SPI1_MOSI.
58 PB6 bidirectional 5 V tolerant GPIO PB6 with I2C1_SCL, TIM4_CH1; remap USART1_TX.
59 PB7 bidirectional 5 V tolerant GPIO PB7 with I2C1_SDA, TIM4_CH2; remap USART1_RX.
60 BOOT0 input Boot mode selection input.
61 PB8 bidirectional 5 V tolerant GPIO PB8 with TIM4_CH3; remap I2C1_SCL, CANRX.
62 PB9 bidirectional 5 V tolerant GPIO PB9 with TIM4_CH4; remap I2C1_SDA, CANTX.
63 VSS_3 power_in Digital ground supply.
64 VDD_3 power_in Digital supply voltage (2.0 to 3.6 V application supply).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32F103R8T7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f103r8t7-etched.step / stm32f103r8t7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f103r8t7.step / stm32f103r8t7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (117 pp, sha256 4741c03c5793745c, retrieved 2026-10-03, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF