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STM32F103R8H7
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), TFBGA-64. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F103R8H7
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · TFBGA-64
STM32F103R8H7 from STMicroelectronics, in a TFBGA-64. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | PC14-OSC32_IN | bidirectional | Backup-domain I/O supplied through the power switch, which sinks only 3 mA, so it may be used as the 32 kHz OSC32_IN and must not be used as a current source or for output above 2 MHz with 30 pF max load. |
| A2 | PC13-TAMPER-RTC | bidirectional | Backup-domain I/O supplied through the power switch, limited to a 3 mA sink, with TAMPER-RTC as alternate function, output speed not to exceed 2 MHz with 30 pF max load, and not to be used as a current source such as an LED driver. |
| A3 | PB9 | bidirectional | 5 V-tolerant I/O with alternate functions TIM4_CH4, I2C1_SDA and CANTX. |
| A4 | PB4 | bidirectional | 5 V-tolerant I/O with alternate functions JNTRST, TIM3_CH1 and SPI1_MISO as listed in Table 5. |
| A5 | PB3 | bidirectional | 5 V-tolerant I/O with alternate functions JTDO, TIM2_CH2, TRACESWO and SPI1_SCK as listed in Table 5. |
| A6 | PA15 | bidirectional | 5 V-tolerant I/O with JTDI as debug alternate function and TIM2_CH1_ETR / SPI1_NSS as remapped alternates. |
| A7 | PA14 | bidirectional | 5 V-tolerant I/O with JTCK/SWCLK as debug alternate function. |
| A8 | PA13 | bidirectional | 5 V-tolerant I/O with JTMS/SWDIO as debug alternate function. |
| B1 | PC15-OSC32_OUT | bidirectional | Backup-domain I/O supplied through the power switch, limited to a 3 mA sink, with OSC32_OUT as alternate function, output speed not to exceed 2 MHz with 30 pF max load, and not to be used as a current source. |
| B2 | VBAT | power_in | Backup supply input for the RTC and backup registers. |
| B3 | PB8 | bidirectional | 5 V-tolerant I/O with alternate functions TIM4_CH3, I2C1_SCL and CANRX. |
| B4 | BOOT0 | input | Boot mode selection input BOOT0 (boot modes are described in Section 2.3.8). |
| B5 | PD2 | bidirectional | 5 V-tolerant I/O with alternate function TIM3_ETR. |
| B6 | PC11 | bidirectional | 5 V-tolerant I/O with alternate function USART3_RX. |
| B7 | PC10 | bidirectional | 5 V-tolerant I/O with alternate function USART3_TX. |
| B8 | PA12 | bidirectional | 5 V-tolerant I/O with alternate functions USART1_RTS, CANTX, USBDP and TIM1_ETR. |
| C1 | OSC_IN | input | External 4-16 MHz crystal oscillator input after reset, which can be remapped to PD0 by software. |
| C2 | VSS_4 | power_in | Digital ground. |
| C3 | PB7 | bidirectional | 5 V-tolerant I/O with alternate functions I2C1_SDA, TIM4_CH2 and USART1_RX. |
| C4 | PB5 | bidirectional | Standard I/O with alternate functions I2C1_SMBAl, TIM3_CH2 and SPI1_MOSI. |
| C5 | PC12 | bidirectional | 5 V-tolerant I/O with alternate function USART3_CK. |
| C6 | PA10 | bidirectional | 5 V-tolerant I/O with alternate functions USART1_RX and TIM1_CH3. |
| C7 | PA9 | bidirectional | 5 V-tolerant I/O with alternate functions USART1_TX and TIM1_CH2. |
| C8 | PA11 | bidirectional | 5 V-tolerant I/O with alternate functions USART1_CTS, CANRX, USBDM and TIM1_CH4. |
| D1 | OSC_OUT | output | External 4-16 MHz crystal oscillator output after reset, which can be remapped to PD1 by software; PD1 in output mode is limited to 50 MHz. |
| D2 | VDD_4 | power_in | Digital supply for I/Os and core, 2.0 to 3.6 V application supply. |
| D3 | PB6 | bidirectional | 5 V-tolerant I/O with alternate functions I2C1_SCL, TIM4_CH1 and USART1_TX. |
| D4 | VSS_3 | power_in | Digital ground. |
| D5 | VSS_2 | power_in | Digital ground. |
| D6 | VSS_1 | power_in | Digital ground. |
| D7 | PA8 | bidirectional | 5 V-tolerant I/O with alternate functions USART1_CK, TIM1_CH1 and MCO. |
| D8 | PC9 | bidirectional | 5 V-tolerant I/O with alternate function TIM3_CH4. |
| E1 | NRST | bidirectional | Reset pin NRST, with electrical characteristics specified in Section 5.3.14. |
| E2 | PC1 | bidirectional | Standard I/O with ADC input ADC12_IN11. |
| E3 | PC0 | bidirectional | Standard I/O with ADC input ADC12_IN10. |
| E4 | VDD_3 | power_in | Digital supply for I/Os and core, 2.0 to 3.6 V application supply. |
| E5 | VDD_2 | power_in | Digital supply for I/Os and core, 2.0 to 3.6 V application supply. |
| E6 | VDD_1 | power_in | Digital supply for I/Os and core, 2.0 to 3.6 V application supply. |
| E7 | PC7 | bidirectional | 5 V-tolerant I/O with alternate function TIM3_CH2. |
| E8 | PC8 | bidirectional | 5 V-tolerant I/O with alternate function TIM3_CH3. |
| F1 | VSSA | power_in | Dedicated analog ground for the ADC. |
| F2 | PC2 | bidirectional | Standard I/O with ADC input ADC12_IN12. |
| F3 | PA2 | bidirectional | Standard I/O with alternate functions USART2_TX, ADC12_IN2 and TIM2_CH3. |
| F4 | PA5 | bidirectional | Standard I/O with alternate functions SPI1_SCK and ADC12_IN5. |
| F5 | PB0 | bidirectional | Standard I/O with alternate functions ADC12_IN8, TIM3_CH3 and TIM1_CH2N. |
| F6 | PC6 | bidirectional | 5 V-tolerant I/O with alternate function TIM3_CH1. |
| F7 | PB15 | bidirectional | 5 V-tolerant I/O with alternate functions SPI2_MOSI and TIM1_CH3N. |
| F8 | PB14 | bidirectional | 5 V-tolerant I/O with alternate functions SPI2_MISO, USART3_RTS and TIM1_CH2N. |
| G1 | VREF+ | power_in | Positive reference voltage input for the ADC, provided on this package in place of PC3. |
| G2 | PA0-WKUP | bidirectional | Standard I/O with wake-up function WKUP and alternate functions USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR. |
| G3 | PA3 | bidirectional | Standard I/O with alternate functions USART2_RX, ADC12_IN3 and TIM2_CH4. |
| G4 | PA6 | bidirectional | Standard I/O with alternate functions SPI1_MISO, ADC12_IN6, TIM3_CH1 and TIM1_BKIN. |
| G5 | PB1 | bidirectional | Standard I/O with alternate functions ADC12_IN9, TIM3_CH4 and TIM1_CH3N. |
| G6 | PB2 | bidirectional | 5 V-tolerant I/O, also serving as BOOT1 (PB2/BOOT1). |
| G7 | PB10 | bidirectional | 5 V-tolerant I/O with alternate functions I2C2_SCL, USART3_TX and TIM2_CH3. |
| G8 | PB13 | bidirectional | 5 V-tolerant I/O with alternate functions SPI2_SCK, USART3_CTS and TIM1_CH1N. |
| H1 | VDDA | power_in | Analog supply for the ADC, with a conversion range of 0 to 3.6 V. |
| H2 | PA1 | bidirectional | Standard I/O with alternate functions USART2_RTS, ADC12_IN1 and TIM2_CH2. |
| H3 | PA4 | bidirectional | Standard I/O with alternate functions SPI1_NSS, USART2_CK and ADC12_IN4. |
| H4 | PA7 | bidirectional | Standard I/O with alternate functions SPI1_MOSI, ADC12_IN7, TIM3_CH2 and TIM1_CH1N. |
| H5 | PC4 | bidirectional | Standard I/O with ADC input ADC12_IN14. |
| H6 | PC5 | bidirectional | Standard I/O with ADC input ADC12_IN15. |
| H7 | PB11 | bidirectional | 5 V-tolerant I/O with alternate functions I2C2_SDA, USART3_RX and TIM2_CH4. |
| H8 | PB12 | bidirectional | 5 V-tolerant I/O with alternate functions SPI2_NSS, I2C2_SMBAl, USART3_CK and TIM1_BKIN. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TFBGA-64 |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32F103R8H7 - Footprint:
Package_BGA:TFBGA-64_5x5mm_Layout8x8_P0.5mm - 3D model: TFBGA-64 (KiCad packages3D, STEP)
- 3D model files:
stm32f103r8h7-etched.step/stm32f103r8h7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f103r8h7.step/stm32f103r8h7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (117 pp, sha256
4741c03c5793745c, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).