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STM32F103CBT7TR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f103cbt7trfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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STM32F103CBT7TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32F103CBT7TR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery backup supply voltage 2.0 to 3.6 V for RTC and backup register domain.
2 PC13 bidirectional GPIO PC13 with power-switch controlled supply (max 3 mA), TAMPER-RTC alternate function.
3 PC14 bidirectional GPIO PC14 with power-switch controlled supply (max 3 mA), OSC32_IN 32.768 kHz oscillator input alternate function.
4 PC15 bidirectional GPIO PC15 with power-switch controlled supply (max 3 mA), OSC32_OUT 32.768 kHz oscillator output alternate function.
5 OSC_IN input High-speed external oscillator 4 to 16 MHz input for main clock and PLL source.
6 OSC_OUT output High-speed external oscillator 4 to 16 MHz output feedback from crystal, remappable to PD1.
7 NRST input Active-low reset input with internal pull-up resistor and debounce filter; remappable with software.
8 VSSA power_in Ground reference for analog circuits including ADC, temperature sensor, and VREF supply.
9 VDDA power_in Analog power supply 2.0 to 3.6 V for ADC and internal voltage reference.
10 PA0 bidirectional GPIO PA0 with wake-up input, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR alternate functions.
11 PA1 bidirectional GPIO PA1 with USART2_RTS, ADC12_IN1, TIM2_CH2 alternate functions.
12 PA2 bidirectional GPIO PA2 with USART2_TX, ADC12_IN2, TIM2_CH3 alternate functions.
13 PA3 bidirectional GPIO PA3 with USART2_RX, ADC12_IN3, TIM2_CH4 alternate functions.
14 PA4 bidirectional GPIO PA4 with SPI1_NSS, USART2_CK, ADC12_IN4 alternate functions.
15 PA5 bidirectional GPIO PA5 with SPI1_SCK and ADC12_IN5 alternate functions.
16 PA6 bidirectional GPIO PA6 with SPI1_MISO, ADC12_IN6, TIM3_CH1 alternate functions; remappable to TIM1_BKIN.
17 PA7 bidirectional GPIO PA7 with SPI1_MOSI, ADC12_IN7, TIM3_CH2 alternate functions; remappable to TIM1_CH1N.
18 PB0 bidirectional GPIO PB0 with ADC12_IN8, TIM3_CH3 alternate functions; remappable to TIM1_CH2N.
19 PB1 bidirectional GPIO PB1 with ADC12_IN9, TIM3_CH4 alternate functions; remappable to TIM1_CH3N.
20 PB2 bidirectional GPIO PB2 with BOOT1 strapping function to select boot from flash or system memory at power-up.
21 PB10 bidirectional GPIO PB10 with I2C2_SCL, USART3_TX, TIM2_CH3 alternate functions.
22 PB11 bidirectional GPIO PB11 with I2C2_SDA, USART3_RX, TIM2_CH4 alternate functions.
23 VSS_1 power_in Ground reference for digital circuits and I/O supply decoupling.
24 VDD_1 power_in Digital power supply 2.0 to 3.6 V for core logic and I/O buffers.
25 PB12 bidirectional GPIO PB12 with SPI2_NSS, I2C2_SMBal, USART3_CK, TIM1_BKIN alternate functions.
26 PB13 bidirectional GPIO PB13 with SPI2_SCK, USART3_CTS, TIM1_CH1N alternate functions.
27 PB14 bidirectional GPIO PB14 with SPI2_MISO, USART3_RTS, TIM1_CH2N alternate functions.
28 PB15 bidirectional GPIO PB15 with SPI2_MOSI, TIM1_CH3N alternate functions.
29 PA8 bidirectional GPIO PA8 with USART1_CK, TIM1_CH1, MCO alternate functions.
30 PA9 bidirectional GPIO PA9 with USART1_TX, TIM1_CH2 alternate functions.
31 PA10 bidirectional GPIO PA10 with USART1_RX, TIM1_CH3 alternate functions.
32 PA11 bidirectional GPIO PA11 with USART1_CTS, CAN_RX, USB_DM, TIM1_CH4 alternate functions.
33 PA12 bidirectional GPIO PA12 with USART1_RTS, CAN_TX, USB_DP, TIM1_ETR alternate functions.
34 PA13 bidirectional JTMS/SWDIO debug interface serial wire data I/O pin; remappable to GPIO PA13.
35 VSS_2 power_in Ground reference for digital circuits and I/O supply decoupling.
36 VDD_2 power_in Digital power supply 2.0 to 3.6 V for core logic and I/O buffers.
37 PA14 bidirectional JTCK/SWCLK debug interface serial wire clock pin; remappable to GPIO PA14.
38 PA15 bidirectional GPIO PA15 with JTDI, TIM2_CH1_ETR, SPI1_NSS alternate functions.
39 PB3 bidirectional GPIO PB3 with JTDO, TIM2_CH2, SPI1_SCK alternate functions; remappable to TRACESWO.
40 PB4 bidirectional GPIO PB4 with JNTRST, TIM3_CH1, SPI1_MISO alternate functions.
41 PB5 bidirectional GPIO PB5 with I2C1_SMBal, TIM3_CH2, SPI1_MOSI alternate functions.
42 PB6 bidirectional GPIO PB6 with I2C1_SCL, TIM4_CH1, USART1_TX alternate functions; 5V-tolerant for USART1_TX.
43 PB7 bidirectional GPIO PB7 with I2C1_SDA, TIM4_CH2, USART1_RX alternate functions; 5V-tolerant for USART1_RX.
44 BOOT0 input Boot configuration input pin: 0 selects boot from flash, 1 selects boot from system memory.
45 PB8 bidirectional GPIO PB8 with TIM4_CH3, I2C1_SCL, CAN_RX alternate functions.
46 PB9 bidirectional GPIO PB9 with TIM4_CH4, I2C1_SDA, CAN_TX alternate functions.
47 VSS_3 power_in Ground reference for digital circuits and I/O supply decoupling.
48 VDD_3 power_in Digital power supply 2.0 to 3.6 V for core logic and I/O buffers.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: STM32F103CBT7TR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f103cbt7tr-etched.step / stm32f103cbt7tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f103cbt7tr.step / stm32f103cbt7tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (117 pp, sha256 e3b559b4227b1427, retrieved 2026-10-06, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF