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3D Model

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Datasheet

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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM32F103C4T6A

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32F103C4T6A from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Backup-domain supply pin for the RTC and backup registers (VBAT supply, per the Features list).
2	PC13-TAMPER-RTC	bidirectional	GPIO PC13 with TAMPER-RTC function; supplied through the power switch, so it sinks at most 3 mA, output speed must not exceed 2 MHz with a 30 pF maximum load, and it must not be used as a current source such as an LED driver.
3	PC14-OSC32_IN	bidirectional	GPIO PC14 with OSC32_IN function; power-switch supplied with the same limits as PC13 (3 mA sink, 2 MHz maximum output speed at 30 pF, not a current source).
4	PC15-OSC32_OUT	bidirectional	GPIO PC15 with OSC32_OUT function; power-switch supplied with the same limits as PC13 (3 mA sink, 2 MHz maximum output speed at 30 pF, not a current source).
5	OSC_IN	input	External oscillator input for the 4 to 16 MHz crystal; after reset this pin is OSC_IN and PD0 can be remapped onto it by software.
6	OSC_OUT	output	External oscillator output for the 4 to 16 MHz crystal; after reset this pin is OSC_OUT and PD1 can be remapped onto it by software.
7	NRST	bidirectional	Active reset pin of the microcontroller, with electrical limits given in the NRST pin characteristics section (5.3.14).
8	VSSA	power_in	Analog ground for the ADC and analog circuitry.
9	VDDA	power_in	Analog supply for the ADC and analog blocks; the ADC conversion range is 0 to 3.6 V and the temperature sensor requires 2 V < VDDA < 3.6 V.
10	PA0-WKUP	bidirectional	GPIO PA0 with WKUP, USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR alternate functions; no 5 V tolerance marking in Table 5.
11	PA1	bidirectional	GPIO PA1 with USART2_RTS, ADC12_IN1 and TIM2_CH2 alternate functions; no 5 V tolerance marking in Table 5.
12	PA2	bidirectional	GPIO PA2 with USART2_TX, ADC12_IN2 and TIM2_CH3 alternate functions; no 5 V tolerance marking in Table 5.
13	PA3	bidirectional	GPIO PA3 with USART2_RX, ADC12_IN3 and TIM2_CH4 alternate functions; no 5 V tolerance marking in Table 5.
14	PA4	bidirectional	GPIO PA4 with SPI1_NSS, USART2_CK and ADC12_IN4 alternate functions; no 5 V tolerance marking in Table 5.
15	PA5	bidirectional	GPIO PA5 with SPI1_SCK and ADC12_IN5 alternate functions; no 5 V tolerance marking in Table 5.
16	PA6	bidirectional	GPIO PA6 with SPI1_MISO, ADC12_IN6 and TIM3_CH1 alternate functions (TIM1_BKIN remap); no 5 V tolerance marking in Table 5.
17	PA7	bidirectional	GPIO PA7 with SPI1_MOSI, ADC12_IN7 and TIM3_CH2 alternate functions (TIM1_CH1N remap); no 5 V tolerance marking in Table 5.
18	PB0	bidirectional	GPIO PB0 with ADC12_IN8 and TIM3_CH3 alternate functions (TIM1_CH2N remap); no 5 V tolerance marking in Table 5.
19	PB1	bidirectional	GPIO PB1 with ADC12_IN9 and TIM3_CH4 alternate functions (TIM1_CH3N remap); no 5 V tolerance marking in Table 5.
20	PB2/BOOT1	bidirectional	GPIO PB2 that also serves as the BOOT1 boot-mode pin; 5 V tolerant (FT) per Table 5.
21	PB10	bidirectional	GPIO PB10 with TIM2_CH3 remap alternate function; 5 V tolerant (FT) per Table 5.
22	PB11	bidirectional	GPIO PB11 with TIM2_CH4 remap alternate function; 5 V tolerant (FT) per Table 5.
23	VSS_1	power_in	Digital ground pin 1 of the device.
24	VDD_1	power_in	Digital supply pin 1; the application supply for I/Os and core is 2.0 to 3.6 V per the Features list.
25	PB12	bidirectional	GPIO PB12 with TIM1_BKIN alternate function; 5 V tolerant (FT) per Table 5.
26	PB13	bidirectional	GPIO PB13 with TIM1_CH1N alternate function; 5 V tolerant (FT) per Table 5.
27	PB14	bidirectional	GPIO PB14 with TIM1_CH2N alternate function; 5 V tolerant (FT) per Table 5.
28	PB15	bidirectional	GPIO PB15 with TIM1_CH3N alternate function; 5 V tolerant (FT) per Table 5.
29	PA8	bidirectional	GPIO PA8 with USART1_CK, TIM1_CH1 and MCO alternate functions; 5 V tolerant (FT) per Table 5.
30	PA9	bidirectional	GPIO PA9 with USART1_TX and TIM1_CH2 alternate functions; 5 V tolerant (FT) per Table 5.
31	PA10	bidirectional	GPIO PA10 with USART1_RX and TIM1_CH3 alternate functions; 5 V tolerant (FT) per Table 5.
32	PA11	bidirectional	GPIO PA11 with USART1_CTS, CAN_RX, TIM1_CH4 and USBDM alternate functions; 5 V tolerant (FT) per Table 5.
33	PA12	bidirectional	GPIO PA12 with USART1_RTS, CAN_TX, TIM1_ETR and USBDP alternate functions; 5 V tolerant (FT) per Table 5.
34	PA13	bidirectional	GPIO PA13 that is also the JTMS/SWDIO debug pin after reset; 5 V tolerant (FT) per Table 5.
35	VSS_2	power_in	Digital ground pin 2 of the device.
36	VDD_2	power_in	Digital supply pin 2; the application supply for I/Os and core is 2.0 to 3.6 V per the Features list.
37	PA14	bidirectional	GPIO PA14 that is also the JTCK/SWCLK debug pin after reset; 5 V tolerant (FT) per Table 5.
38	PA15	bidirectional	GPIO PA15 that is also the JTDI debug pin after reset, with TIM2_CH1_ETR and SPI1_NSS remap alternate functions; 5 V tolerant (FT) per Table 5.
39	PB3	bidirectional	GPIO PB3 that is also the JTDO debug pin after reset, with TIM2_CH2 and TRACESWO remap alternate functions; 5 V tolerant (FT) per Table 5.
40	PB4	bidirectional	GPIO PB4 that is also the NJTRST debug pin after reset, with TIM3_CH1 and SPI1_MISO remap alternate functions; 5 V tolerant (FT) per Table 5.
41	PB5	bidirectional	GPIO PB5 with I2C1_SMBA alternate function and TIM3_CH2 and SPI1_MOSI remap options; no 5 V tolerance marking in Table 5.
42	PB6	bidirectional	GPIO PB6 with I2C1_SCL and USART1_TX alternate functions; 5 V tolerant (FT) per Table 5.
43	PB7	bidirectional	GPIO PB7 with I2C1_SDA and USART1_RX alternate functions; 5 V tolerant (FT) per Table 5.
44	BOOT0	input	Boot-mode selection input BOOT0 (listed as an input without 5 V tolerance in Table 5).
45	PB8	bidirectional	GPIO PB8 with I2C1_SCL and CAN_RX remap alternate functions; 5 V tolerant (FT) per Table 5.
46	PB9	bidirectional	GPIO PB9 with I2C1_SDA and CAN_TX remap alternate functions; 5 V tolerant (FT) per Table 5.
47	VSS_3	power_in	Digital ground pin 3 of the device.
48	VDD_3	power_in	Digital supply pin 3; the application supply for I/Os and core is 2.0 to 3.6 V per the Features list.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

CAD (KiCad official)

Symbol: STM32F103C4T6A
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: stm32f103c4t6a-etched.step / stm32f103c4t6a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f103c4t6a.step / stm32f103c4t6a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (99 pp, sha256 31ab1fe3de6e6cf3, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF