# STM32F102RBT6

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F102RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply input that powers the RTC and backup registers. |
| 2 | PC13-TAMPER-RTC | bidirectional | I/O PC13 (main function after first backup-domain power-up) with TAMPER-RTC alternate function; it is supplied through the power switch, which sinks at most 3 mA, so speed must not exceed 2 MHz at 30 pF and it must not source current such as driving an LED. |
| 3 | PC14-OSC32_IN | bidirectional | I/O PC14 (main function after first backup-domain power-up) or OSC32_IN for the 32 kHz oscillator, with the same power-switch limits as PC13 (3 mA sink, 2 MHz at 30 pF, no current sourcing). |
| 4 | PC15-OSC32_OUT | bidirectional | I/O PC15 (main function after first backup-domain power-up) or OSC32_OUT for the 32 kHz oscillator, with the same power-switch limits as PC13 (3 mA sink, 2 MHz at 30 pF, no current sourcing). |
| 5 | PD0-OSC_IN | bidirectional | 5 V-tolerant pin configured as OSC_IN after reset, with PD0 remappable by software and PD0 limited to 50 MHz when used as an output. |
| 6 | PD1-OSC_OUT | bidirectional | 5 V-tolerant pin configured as OSC_OUT after reset, with PD1 remappable by software and PD1 limited to 50 MHz when used as an output. |
| 7 | NRST | bidirectional | Bidirectional NRST reset pin whose electrical characteristics are specified in Section 5.3.14 of the datasheet. |
| 8 | PC0 | bidirectional | Standard (not 5 V-tolerant) general-purpose I/O PC0, also usable as ADC_IN10. |
| 9 | PC1 | bidirectional | Standard (not 5 V-tolerant) general-purpose I/O PC1, also usable as ADC_IN11. |
| 10 | PC2 | bidirectional | Standard (not 5 V-tolerant) general-purpose I/O PC2, also usable as ADC_IN12. |
| 11 | PC3 | bidirectional | Standard (not 5 V-tolerant) general-purpose I/O PC3, also usable as ADC_IN13. |
| 12 | VSSA | power_in | Analog ground for the ADC and analog circuitry, referenced to VSS. |
| 13 | VDDA | power_in | Analog supply for the ADC and analog blocks; the temperature sensor conversion range requires 2 V < VDDA < 3.6 V. |
| 14 | PA0-WKUP | bidirectional | Standard I/O PA0 with WKUP wake-up, USART2_CTS, ADC_IN0 and TIM2_CH1_ETR alternate functions. |
| 15 | PA1 | bidirectional | Standard I/O PA1 with USART2_RTS, ADC_IN1 and TIM2_CH2 alternate functions. |
| 16 | PA2 | bidirectional | Standard I/O PA2 with USART2_TX, ADC_IN2 and TIM2_CH3 alternate functions. |
| 17 | PA3 | bidirectional | Standard I/O PA3 with USART2_RX, ADC_IN3 and TIM2_CH4 alternate functions. |
| 18 | VSS_4 | power_in | Ground pin for the digital logic and I/Os, referenced to VSS. |
| 19 | VDD_4 | power_in | Digital supply pin for the I/Os and logic, within the 2.0 to 3.6 V application supply range. |
| 20 | PA4 | bidirectional | Standard I/O PA4 with SPI1_NSS and ADC_IN4 alternate functions. |
| 21 | PA5 | bidirectional | Standard I/O PA5 with SPI1_SCK and ADC_IN5 alternate functions. |
| 22 | PA6 | bidirectional | Standard I/O PA6 with SPI1_MISO, ADC_IN6 and TIM3_CH1 alternate functions. |
| 23 | PA7 | bidirectional | Standard I/O PA7 with SPI1_MOSI, ADC_IN7 and TIM3_CH2 alternate functions. |
| 24 | PC4 | bidirectional | Standard I/O PC4, also usable as ADC_IN14. |
| 25 | PC5 | bidirectional | Standard I/O PC5, also usable as ADC_IN15. |
| 26 | PB0 | bidirectional | Standard I/O PB0 with ADC_IN8 and TIM3_CH3 alternate functions. |
| 27 | PB1 | bidirectional | Standard I/O PB1 with ADC_IN9 and TIM3_CH4 alternate functions. |
| 28 | PB2/BOOT1 | bidirectional | 5 V-tolerant (FT) I/O PB2, which also serves as the BOOT1 boot-mode pin. |
| 29 | PB10 | bidirectional | 5 V-tolerant (FT) I/O PB10 with I2C2_SCL, USART3_TX and TIM2_CH3 alternate functions. |
| 30 | PB11 | bidirectional | 5 V-tolerant (FT) I/O PB11 with I2C2_SDA, USART3_RX and TIM2_CH4 alternate functions. |
| 31 | VSS_1 | power_in | Ground pin for the digital logic and I/Os, referenced to VSS. |
| 32 | VDD_1 | power_in | Digital supply pin for the I/Os and logic, within the 2.0 to 3.6 V application supply range. |
| 33 | PB12 | bidirectional | 5 V-tolerant (FT) I/O PB12 with SPI2_NSS, I2C2_SMBA and USART3_CK alternate functions. |
| 34 | PB13 | bidirectional | 5 V-tolerant (FT) I/O PB13 with SPI2_SCK and USART3_CTS alternate functions. |
| 35 | PB14 | bidirectional | 5 V-tolerant (FT) I/O PB14 with SPI2_MISO and USART3_RTS alternate functions. |
| 36 | PB15 | bidirectional | 5 V-tolerant (FT) I/O PB15 with SPI2_MOSI alternate function. |
| 37 | PC6 | bidirectional | 5 V-tolerant (FT) I/O PC6 with TIM3_CH1 alternate function. |
| 38 | PC7 | bidirectional | 5 V-tolerant (FT) I/O PC7 with TIM3_CH2 alternate function. |
| 39 | PC8 | bidirectional | 5 V-tolerant (FT) I/O PC8 with TIM3_CH3 alternate function. |
| 40 | PC9 | bidirectional | 5 V-tolerant (FT) I/O PC9 with TIM3_CH4 alternate function. |
| 41 | PA8 | bidirectional | 5 V-tolerant (FT) I/O PA8 with USART1_CK and MCO alternate functions. |
| 42 | PA9 | bidirectional | 5 V-tolerant (FT) I/O PA9 with USART1_TX alternate function. |
| 43 | PA10 | bidirectional | 5 V-tolerant (FT) I/O PA10 with USART1_RX alternate function. |
| 44 | PA11 | bidirectional | 5 V-tolerant (FT) I/O PA11 with USART1_CTS and USB_DM alternate functions. |
| 45 | PA12 | bidirectional | 5 V-tolerant (FT) I/O PA12 with USART1_RTS and USB_DP alternate functions. |
| 46 | PA13 | bidirectional | 5 V-tolerant (FT) I/O PA13 that serves as the JTMS-SWDIO debug pin. |
| 47 | VSS_2 | power_in | Ground pin for the digital logic and I/Os, referenced to VSS. |
| 48 | VDD_2 | power_in | Digital supply pin for the I/Os and logic, within the 2.0 to 3.6 V application supply range. |
| 49 | PA14 | bidirectional | 5 V-tolerant (FT) I/O PA14 that serves as the JTCK-SWCLK debug pin. |
| 50 | PA15 | bidirectional | 5 V-tolerant (FT) I/O PA15 with JTDI, TIM2_CH1_ETR and SPI1_NSS alternate functions. |
| 51 | PC10 | bidirectional | 5 V-tolerant (FT) I/O PC10 with USART3_TX alternate function. |
| 52 | PC11 | bidirectional | 5 V-tolerant (FT) I/O PC11 with USART3_RX alternate function. |
| 53 | PC12 | bidirectional | 5 V-tolerant (FT) I/O PC12 with USART3_CK alternate function. |
| 54 | PD2 | bidirectional | 5 V-tolerant (FT) I/O PD2 with TIM3_ETR alternate function. |
| 55 | PB3 | bidirectional | 5 V-tolerant (FT) I/O PB3 with JTDO, TRACESWO, TIM2_CH2 and SPI1_SCK alternate functions. |
| 56 | PB4 | bidirectional | 5 V-tolerant (FT) I/O PB4 with JNTRST, TIM3_CH1 and SPI1_MISO alternate functions. |
| 57 | PB5 | bidirectional | Standard I/O PB5 with I2C1_SMBA, TIM3_CH2 and SPI1_MOSI alternate functions. |
| 58 | PB6 | bidirectional | 5 V-tolerant (FT) I/O PB6 with I2C1_SCL, TIM4_CH1 and USART1_TX alternate functions. |
| 59 | PB7 | bidirectional | 5 V-tolerant (FT) I/O PB7 with I2C1_SDA, TIM4_CH2 and USART1_RX alternate functions. |
| 60 | BOOT0 | input | Boot mode selection input that, together with BOOT1, determines whether the memory is aliased to Flash or system memory. |
| 61 | PB8 | bidirectional | 5 V-tolerant (FT) I/O PB8 with TIM4_CH3 and I2C1_SCL alternate functions. |
| 62 | PB9 | bidirectional | 5 V-tolerant (FT) I/O PB9 with TIM4_CH4 and I2C1_SDA alternate functions. |
| 63 | VSS_3 | power_in | Ground pin for the digital logic and I/Os, referenced to VSS. |
| 64 | VDD_3 | power_in | Digital supply pin for the I/Os and logic, within the 2.0 to 3.6 V application supply range. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## CAD (KiCad official)

- Symbol: `STM32F102RBT6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `stm32f102rbt6-etched.step` / `stm32f102rbt6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32f102rbt6.step` / `stm32f102rbt6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893448576880640) (81 pp, sha256 `276652841a00ce34`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32f102rbt6-datasheet.pdf)