# STM32F101VFT6

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F101VFT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V-tolerant (FT) I/O port E bit 2; alternate functions TRACECLK and FSMC_A23. |
| 2 | PE3 | bidirectional | 5 V-tolerant (FT) I/O port E bit 3; alternate functions TRACED0 and FSMC_A19. |
| 3 | PE4 | bidirectional | 5 V-tolerant (FT) I/O port E bit 4; alternate functions TRACED1 and FSMC_A20. |
| 4 | PE5 | bidirectional | 5 V-tolerant (FT) I/O port E bit 5; alternate functions TRACED2, FSMC_A21 and TIM9_CH1. |
| 5 | PE6 | bidirectional | 5 V-tolerant (FT) I/O port E bit 6; alternate functions TRACED3, FSMC_A22 and TIM9_CH2. |
| 6 | VBAT | power_in | Backup-domain supply input for the RTC and backup registers (VBAT supply). |
| 7 | PC13-TAMPER-RTC | bidirectional | I/O supplied through the power switch, which sinks only 3 mA, so use is limited to 2 MHz with a 30 pF maximum load and it must not source current (e.g. drive an LED); alternate function TAMPER-RTC. |
| 8 | PC14-OSC32_IN | bidirectional | I/O supplied through the power switch (3 mA limit; max 2 MHz at 30 pF, no current sourcing); alternate function OSC32_IN. |
| 9 | PC15-OSC32_OUT | bidirectional | I/O supplied through the power switch (3 mA limit; max 2 MHz at 30 pF, no current sourcing); alternate function OSC32_OUT. |
| 10 | VSS_5 | power_in | Digital ground pin for the device. |
| 11 | VDD_5 | power_in | Digital supply pin, part of the 2.0 to 3.6 V application supply and I/Os. |
| 12 | OSC_IN | input | Input of the 4-to-16 MHz crystal oscillator (HSE). |
| 13 | OSC_OUT | output | Output of the 4-to-16 MHz crystal oscillator (HSE). |
| 14 | NRST | bidirectional | Reset pin; its electrical characteristics are given in section 5.3.15 (NRST pin characteristics). |
| 15 | PC0 | bidirectional | Standard I/O port C bit 0 (not marked 5 V tolerant in Table 5) with alternate function ADC_IN10. |
| 16 | PC1 | bidirectional | Standard I/O port C bit 1 (not marked 5 V tolerant in Table 5) with alternate function ADC_IN11. |
| 17 | PC2 | bidirectional | Standard I/O port C bit 2 (not marked 5 V tolerant in Table 5) with alternate function ADC_IN12. |
| 18 | PC3 | bidirectional | Standard I/O port C bit 3 (not marked 5 V tolerant in Table 5) with alternate function ADC_IN13. |
| 19 | VSSA | power_in | Analog ground reference for the analog circuitry (ADC and reference). |
| 20 | VREF- | power_in | ADC negative reference voltage; it may be internally connected to VSSA depending on the package. |
| 21 | VREF+ | power_in | ADC positive reference voltage, 2.4 V to VDDA; it may be internally connected to VDDA depending on the package. |
| 22 | VDDA | power_in | Analog supply for the ADC, 2.4 V to 3.6 V (Table 55). |
| 23 | PA0-WKUP | bidirectional | Standard I/O port A bit 0 (not marked 5 V tolerant in Table 5); alternate functions WKUP, USART2_CTS, ADC_IN0, TIM5_CH1 and TIM2_CH1_ETR. |
| 24 | PA1 | bidirectional | Standard I/O port A bit 1 (not marked 5 V tolerant in Table 5); alternate functions USART2_RTS, ADC_IN1, TIM5_CH2 and TIM2_CH2. |
| 25 | PA2 | bidirectional | Standard I/O port A bit 2 (not marked 5 V tolerant in Table 5); alternate functions USART2_TX, TIM5_CH3, ADC_IN2, TIM2_CH3 and TIM9_CH1. |
| 26 | PA3 | bidirectional | Standard I/O port A bit 3 (not marked 5 V tolerant in Table 5); alternate functions USART2_RX, TIM5_CH4, ADC_IN3, TIM2_CH4 and TIM9_CH2. |
| 27 | VSS_4 | power_in | Digital ground pin for the device. |
| 28 | VDD_4 | power_in | Digital supply pin, part of the 2.0 to 3.6 V application supply and I/Os. |
| 29 | PA4 | bidirectional | Standard I/O port A bit 4 (not marked 5 V tolerant in Table 5); alternate functions SPI1_NSS, DAC_OUT1, ADC_IN4 and USART2_CK. |
| 30 | PA5 | bidirectional | Standard I/O port A bit 5 (not marked 5 V tolerant in Table 5); alternate functions SPI1_SCK, DAC_OUT2 and ADC_IN5. |
| 31 | PA6 | bidirectional | Standard I/O port A bit 6 (not marked 5 V tolerant in Table 5); alternate functions SPI1_MISO, ADC_IN6, TIM3_CH1 and TIM13_CH1. |
| 32 | PA7 | bidirectional | Standard I/O port A bit 7 (not marked 5 V tolerant in Table 5); alternate functions SPI1_MOSI, ADC_IN7, TIM3_CH2 and TIM14_CH1. |
| 33 | PC4 | bidirectional | Standard I/O port C bit 4 (not marked 5 V tolerant in Table 5) with alternate function ADC_IN14. |
| 34 | PC5 | bidirectional | Standard I/O port C bit 5 (not marked 5 V tolerant in Table 5) with alternate function ADC_IN15. |
| 35 | PB0 | bidirectional | Standard I/O port B bit 0 (not marked 5 V tolerant in Table 5); alternate functions ADC_IN8 and TIM3_CH3. |
| 36 | PB1 | bidirectional | Standard I/O port B bit 1 (not marked 5 V tolerant in Table 5); alternate functions ADC_IN9 and TIM3_CH4. |
| 37 | PB2 | bidirectional | 5 V-tolerant (FT) I/O port B bit 2, also functioning as BOOT1. |
| 38 | PE7 | bidirectional | 5 V-tolerant (FT) I/O port E bit 7; alternate function FSMC_D4. |
| 39 | PE8 | bidirectional | 5 V-tolerant (FT) I/O port E bit 8; alternate function FSMC_D5. |
| 40 | PE9 | bidirectional | 5 V-tolerant (FT) I/O port E bit 9; alternate function FSMC_D6. |
| 41 | PE10 | bidirectional | 5 V-tolerant (FT) I/O port E bit 10; alternate function FSMC_D7. |
| 42 | PE11 | bidirectional | 5 V-tolerant (FT) I/O port E bit 11; alternate function FSMC_D8. |
| 43 | PE12 | bidirectional | 5 V-tolerant (FT) I/O port E bit 12; alternate function FSMC_D9. |
| 44 | PE13 | bidirectional | 5 V-tolerant (FT) I/O port E bit 13; alternate function FSMC_D10. |
| 45 | PE14 | bidirectional | 5 V-tolerant (FT) I/O port E bit 14; alternate function FSMC_D11. |
| 46 | PE15 | bidirectional | 5 V-tolerant (FT) I/O port E bit 15; alternate function FSMC_D12. |
| 47 | PB10 | bidirectional | 5 V-tolerant (FT) I/O port B bit 10; alternate functions I2C2_SCL, USART3_TX and TIM2_CH3. |
| 48 | PB11 | bidirectional | 5 V-tolerant (FT) I/O port B bit 11; alternate functions I2C2_SDA, USART3_RX and TIM2_CH4. |
| 49 | VSS_1 | power_in | Digital ground pin for the device. |
| 50 | VDD_1 | power_in | Digital supply pin, part of the 2.0 to 3.6 V application supply and I/Os. |
| 51 | PB12 | bidirectional | 5 V-tolerant (FT) I/O port B bit 12; alternate functions SPI2_NSS, I2C2_SMBA and USART3_CK. |
| 52 | PB13 | bidirectional | 5 V-tolerant (FT) I/O port B bit 13; alternate functions SPI2_SCK and USART3_CTS. |
| 53 | PB14 | bidirectional | 5 V-tolerant (FT) I/O port B bit 14; alternate functions SPI2_MISO, USART3_RTS and TIM12_CH1. |
| 54 | PB15 | bidirectional | 5 V-tolerant (FT) I/O port B bit 15; alternate functions SPI2_MOSI and TIM12_CH2. |
| 55 | PD8 | bidirectional | 5 V-tolerant (FT) I/O port D bit 8; alternate functions FSMC_D13 and USART3_TX. |
| 56 | PD9 | bidirectional | 5 V-tolerant (FT) I/O port D bit 9; alternate functions FSMC_D14 and USART3_RX. |
| 57 | PD10 | bidirectional | 5 V-tolerant (FT) I/O port D bit 10; alternate functions FSMC_D15 and USART3_CK. |
| 58 | PD11 | bidirectional | 5 V-tolerant (FT) I/O port D bit 11; alternate functions FSMC_A16 and USART3_CTS. |
| 59 | PD12 | bidirectional | 5 V-tolerant (FT) I/O port D bit 12; alternate functions FSMC_A17, TIM4_CH1 and USART3_RTS. |
| 60 | PD13 | bidirectional | 5 V-tolerant (FT) I/O port D bit 13; alternate functions FSMC_A18 and TIM4_CH2. |
| 61 | PD14 | bidirectional | 5 V-tolerant (FT) I/O port D bit 14; alternate functions FSMC_D0 and TIM4_CH3. |
| 62 | PD15 | bidirectional | 5 V-tolerant (FT) I/O port D bit 15; alternate functions FSMC_D1 and TIM4_CH4. |
| 63 | PC6 | bidirectional | 5 V-tolerant (FT) I/O port C bit 6; alternate function TIM3_CH1. |
| 64 | PC7 | bidirectional | 5 V-tolerant (FT) I/O port C bit 7; alternate function TIM3_CH2. |
| 65 | PC8 | bidirectional | 5 V-tolerant (FT) I/O port C bit 8; alternate function TIM3_CH3. |
| 66 | PC9 | bidirectional | 5 V-tolerant (FT) I/O port C bit 9; alternate function TIM3_CH4. |
| 67 | PA8 | bidirectional | 5 V-tolerant (FT) I/O port A bit 8; alternate functions USART1_CK and MCO. |
| 68 | PA9 | bidirectional | 5 V-tolerant (FT) I/O port A bit 9; alternate function USART1_TX. |
| 69 | PA10 | bidirectional | 5 V-tolerant (FT) I/O port A bit 10; alternate function USART1_RX. |
| 70 | PA11 | bidirectional | 5 V-tolerant (FT) I/O port A bit 11; alternate function USART1_CTS. |
| 71 | PA12 | bidirectional | 5 V-tolerant (FT) I/O port A bit 12; alternate function USART1_RTS. |
| 72 | PA13 | bidirectional | 5 V-tolerant (FT) I/O port A bit 13; default function JTMS-SWDIO (serial wire debug). |
| 73 | NC | unconnected | Not connected on the LQFP100 package. |
| 74 | VSS_2 | power_in | Digital ground pin for the device. |
| 75 | VDD_2 | power_in | Digital supply pin, part of the 2.0 to 3.6 V application supply and I/Os. |
| 76 | PA14 | bidirectional | 5 V-tolerant (FT) I/O port A bit 14; default function JTCK-SWCLK (serial wire debug). |
| 77 | PA15 | bidirectional | 5 V-tolerant (FT) I/O; default function JTDI, with alternate functions SPI3_NSS, TIM2_CH1_ETR and SPI1_NSS. |
| 78 | PC10 | bidirectional | 5 V-tolerant (FT) I/O port C bit 10; alternate functions UART4_TX and USART3_TX. |
| 79 | PC11 | bidirectional | 5 V-tolerant (FT) I/O port C bit 11; alternate functions UART4_RX and USART3_RX. |
| 80 | PC12 | bidirectional | 5 V-tolerant (FT) I/O port C bit 12; alternate functions UART5_TX and USART3_CK. |
| 81 | PD0 | bidirectional | 5 V-tolerant (FT) I/O port D bit 0, available by default on LQFP100 (no remap needed); alternate functions OSC_IN and FSMC_D2. |
| 82 | PD1 | bidirectional | 5 V-tolerant (FT) I/O port D bit 1, available by default on LQFP100 (no remap needed); alternate functions OSC_OUT and FSMC_D3. |
| 83 | PD2 | bidirectional | 5 V-tolerant (FT) I/O port D bit 2; alternate functions TIM3_ETR and UART5_RX. |
| 84 | PD3 | bidirectional | 5 V-tolerant (FT) I/O port D bit 3; alternate functions FSMC_CLK and USART2_CTS. |
| 85 | PD4 | bidirectional | 5 V-tolerant (FT) I/O port D bit 4; alternate functions FSMC_NOE and USART2_RTS. |
| 86 | PD5 | bidirectional | 5 V-tolerant (FT) I/O port D bit 5; alternate functions FSMC_NWE and USART2_TX. |
| 87 | PD6 | bidirectional | 5 V-tolerant (FT) I/O port D bit 6; alternate functions FSMC_NWAIT and USART2_RX. |
| 88 | PD7 | bidirectional | 5 V-tolerant (FT) I/O port D bit 7; alternate functions FSMC_NE1 / FSMC_NCE2 and USART2_CK. |
| 89 | PB3 | bidirectional | 5 V-tolerant (FT) I/O port B bit 3; default function JTDO, with alternate functions SPI3_SCK, TIM2_CH2, TRACESWO and SPI1_SCK. |
| 90 | PB4 | bidirectional | 5 V-tolerant (FT) I/O port B bit 4; default function NJTRST, with alternate functions SPI3_MISO, TIM3_CH1 and SPI1_MISO. |
| 91 | PB5 | bidirectional | Standard I/O port B bit 5 (not marked 5 V tolerant in Table 5); alternate functions I2C1_SMBA, SPI3_MOSI, TIM3_CH2 and SPI1_MOSI. |
| 92 | PB6 | bidirectional | 5 V-tolerant (FT) I/O port B bit 6; alternate functions I2C1_SCL, TIM4_CH1 and USART1_TX. |
| 93 | PB7 | bidirectional | 5 V-tolerant (FT) I/O port B bit 7; alternate functions I2C1_SDA, FSMC_NADV, TIM4_CH2 and USART1_RX. |
| 94 | BOOT0 | input | Boot mode selection input; the memory map aliases Flash or system memory depending on the BOOT pins. |
| 95 | PB8 | bidirectional | 5 V-tolerant (FT) I/O port B bit 8; alternate functions TIM4_CH3 and I2C1_SCL. |
| 96 | PB9 | bidirectional | 5 V-tolerant (FT) I/O port B bit 9; alternate functions TIM4_CH4 and I2C1_SDA. |
| 97 | PE0 | bidirectional | 5 V-tolerant (FT) I/O port E bit 0; alternate functions TIM4_ETR and FSMC_NBL0. |
| 98 | PE1 | bidirectional | 5 V-tolerant (FT) I/O port E bit 1; alternate function FSMC_NBL1. |
| 99 | VSS_3 | power_in | Digital ground pin for the device. |
| 100 | VDD_3 | power_in | Digital supply pin, part of the 2.0 to 3.6 V application supply and I/Os. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## CAD (KiCad official)

- Symbol: `STM32F101VFT6`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `stm32f101vft6-etched.step` / `stm32f101vft6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32f101vft6.step` / `stm32f101vft6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586181449480851456) (108 pp, sha256 `18cfb115c8781336`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32f101vft6-datasheet.pdf)