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STM32F101VET6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f101vet6factory-2.0.0extractor-text
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Symbol & Footprint

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Datasheet

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Contents

README

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STM32F101VET6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F101VET6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional General-purpose I/O (5 V tolerant, FT) with alternate functions TRACECLK or FSMC_A23.
2 PE3 bidirectional General-purpose I/O (5 V tolerant, FT) with alternate functions TRACED0 or FSMC_A19.
3 PE4 bidirectional General-purpose I/O (5 V tolerant, FT) with alternate functions TRACED1 or FSMC_A20.
4 PE5 bidirectional General-purpose I/O (5 V tolerant, FT) with alternate functions TRACED2 or FSMC_A21.
5 PE6 bidirectional General-purpose I/O (5 V tolerant, FT) with alternate functions TRACED3 or FSMC_A22.
6 VBAT power_in Backup-domain supply for the RTC and backup registers.
7 PC13-TAMPER-RTC bidirectional GPIO PC13 supplied through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz at 30 pF and it must not source current such as driving an LED; TAMPER-RTC function.
8 PC14-OSC32_IN bidirectional GPIO PC14 with the same power-switch limits (3 mA, 2 MHz at 30 pF, no current sourcing); OSC32_IN for the 32.768 kHz oscillator.
9 PC15-OSC32_OUT bidirectional GPIO PC15 with the same power-switch limits (3 mA, 2 MHz at 30 pF, no current sourcing); OSC32_OUT for the 32.768 kHz oscillator.
10 VSS_5 power_in Digital ground.
11 VDD_5 power_in Digital supply for I/Os and core, 2.0 to 3.6 V application supply.
12 OSC_IN input External 4 to 16 MHz crystal oscillator input (HSE).
13 OSC_OUT output External 4 to 16 MHz crystal oscillator output (HSE).
14 NRST bidirectional Device reset pin (NRST).
15 PC0 bidirectional GPIO PC0 not marked 5 V tolerant in Table 5; ADC_IN10 analog input.
16 PC1 bidirectional GPIO PC1 not marked 5 V tolerant in Table 5; ADC_IN11 analog input.
17 PC2 bidirectional GPIO PC2 not marked 5 V tolerant in Table 5; ADC_IN12 analog input.
18 PC3 bidirectional GPIO PC3 not marked 5 V tolerant in Table 5; ADC_IN13 analog input.
19 VSSA power_in Analog ground.
20 VREF- power_in ADC negative reference, which can be internally connected to VSSA depending on the package.
21 VREF+ power_in ADC positive reference, 2.4 V up to VDDA.
22 VDDA power_in Analog supply for the ADC, 2.4 to 3.6 V.
23 PA0-WKUP bidirectional GPIO PA0 with WKUP wake-up function; alternate functions USART2_CTS, ADC_IN0, TIM5_CH1 and TIM2_CH1_ETR.
24 PA1 bidirectional GPIO PA1 with alternate functions USART2_RTS, ADC_IN1, TIM5_CH2 and TIM2_CH2.
25 PA2 bidirectional GPIO PA2 with alternate functions USART2_TX, TIM5_CH3, ADC_IN2 and TIM2_CH3.
26 PA3 bidirectional GPIO PA3 with alternate functions USART2_RX, TIM5_CH4, ADC_IN3 and TIM2_CH4.
27 VSS_4 power_in Digital ground.
28 VDD_4 power_in Digital supply for I/Os and core, 2.0 to 3.6 V application supply.
29 PA4 bidirectional GPIO PA4 with alternate functions SPI1_NSS, DAC_OUT1, ADC_IN4 and USART2_CK.
30 PA5 bidirectional GPIO PA5 with alternate functions SPI1_SCK, DAC_OUT2 and ADC_IN5.
31 PA6 bidirectional GPIO PA6 with alternate functions SPI1_MISO, ADC_IN6 and TIM3_CH1.
32 PA7 bidirectional GPIO PA7 with alternate functions SPI1_MOSI, ADC_IN7 and TIM3_CH2.
33 PC4 bidirectional GPIO PC4 with ADC_IN14 analog input.
34 PC5 bidirectional GPIO PC5 with ADC_IN15 analog input.
35 PB0 bidirectional GPIO PB0 with alternate functions ADC_IN8 and TIM3_CH3.
36 PB1 bidirectional GPIO PB1 with alternate functions ADC_IN9 and TIM3_CH4.
37 PB2 bidirectional GPIO PB2 (5 V tolerant, FT), also the BOOT1 boot-mode pin.
38 PE7 bidirectional GPIO PE7 (5 V tolerant, FT) with FSMC_D4 alternate function.
39 PE8 bidirectional GPIO PE8 (5 V tolerant, FT) with FSMC_D5 alternate function.
40 PE9 bidirectional GPIO PE9 (5 V tolerant, FT) with FSMC_D6 alternate function.
41 PE10 bidirectional GPIO PE10 (5 V tolerant, FT) with FSMC_D7 alternate function.
42 PE11 bidirectional GPIO PE11 (5 V tolerant, FT) with FSMC_D8 alternate function.
43 PE12 bidirectional GPIO PE12 (5 V tolerant, FT) with FSMC_D9 alternate function.
44 PE13 bidirectional GPIO PE13 (5 V tolerant, FT) with FSMC_D10 alternate function.
45 PE14 bidirectional GPIO PE14 (5 V tolerant, FT) with FSMC_D11 alternate function.
46 PE15 bidirectional GPIO PE15 (5 V tolerant, FT) with FSMC_D12 alternate function.
47 PB10 bidirectional GPIO PB10 (5 V tolerant, FT) with alternate functions I2C2_SCL, USART3_TX and TIM2_CH3.
48 PB11 bidirectional GPIO PB11 (5 V tolerant, FT) with alternate functions I2C2_SDA, USART3_RX and TIM2_CH4.
49 VSS_1 power_in Digital ground.
50 VDD_1 power_in Digital supply for I/Os and core, 2.0 to 3.6 V application supply.
51 PB12 bidirectional GPIO PB12 (5 V tolerant, FT) with alternate functions SPI2_NSS, I2C2_SMBA and USART3_CK.
52 PB13 bidirectional GPIO PB13 (5 V tolerant, FT) with alternate functions SPI2_SCK and USART3_CTS.
53 PB14 bidirectional GPIO PB14 (5 V tolerant, FT) with alternate functions SPI2_MISO and USART3_RTS.
54 PB15 bidirectional GPIO PB15 (5 V tolerant, FT) with alternate function SPI2_MOSI.
55 PD8 bidirectional GPIO PD8 (5 V tolerant, FT) with alternate functions FSMC_D13 and USART3_TX.
56 PD9 bidirectional GPIO PD9 (5 V tolerant, FT) with alternate functions FSMC_D14 and USART3_RX.
57 PD10 bidirectional GPIO PD10 (5 V tolerant, FT) with alternate functions FSMC_D15 and USART3_CK.
58 PD11 bidirectional GPIO PD11 (5 V tolerant, FT) with alternate functions FSMC_A16 and USART3_CTS.
59 PD12 bidirectional GPIO PD12 (5 V tolerant, FT) with alternate functions FSMC_A17, TIM4_CH1 and USART3_RTS.
60 PD13 bidirectional GPIO PD13 (5 V tolerant, FT) with alternate functions FSMC_A18 and TIM4_CH2.
61 PD14 bidirectional GPIO PD14 (5 V tolerant, FT) with alternate functions FSMC_D0 and TIM4_CH3.
62 PD15 bidirectional GPIO PD15 (5 V tolerant, FT) with alternate functions FSMC_D1 and TIM4_CH4.
63 PC6 bidirectional GPIO PC6 (5 V tolerant, FT) with alternate function TIM3_CH1.
64 PC7 bidirectional GPIO PC7 (5 V tolerant, FT) with alternate function TIM3_CH2.
65 PC8 bidirectional GPIO PC8 (5 V tolerant, FT) with alternate function TIM3_CH3.
66 PC9 bidirectional GPIO PC9 (5 V tolerant, FT) with alternate function TIM3_CH4.
67 PA8 bidirectional GPIO PA8 (5 V tolerant, FT) with alternate functions USART1_CK and MCO.
68 PA9 bidirectional GPIO PA9 (5 V tolerant, FT) with alternate function USART1_TX.
69 PA10 bidirectional GPIO PA10 (5 V tolerant, FT) with alternate function USART1_RX.
70 PA11 bidirectional GPIO PA11 (5 V tolerant, FT) with alternate function USART1_CTS.
71 PA12 bidirectional GPIO PA12 (5 V tolerant, FT) with alternate function USART1_RTS.
72 PA13 bidirectional GPIO PA13 (5 V tolerant, FT); default function JTMS-SWDIO.
73 NC unconnected Not connected on the LQFP100 package.
74 VSS_2 power_in Digital ground.
75 VDD_2 power_in Digital supply for I/Os and core, 2.0 to 3.6 V application supply.
76 PA14 bidirectional GPIO PA14 (5 V tolerant, FT); default function JTCK-SWCLK.
77 PA15 bidirectional GPIO PA15 (5 V tolerant, FT) with alternate functions JTDI, SPI3_NSS, TIM2_CH1_ETR and SPI1_NSS.
78 PC10 bidirectional GPIO PC10 (5 V tolerant, FT) with alternate functions UART4_TX and USART3_TX.
79 PC11 bidirectional GPIO PC11 (5 V tolerant, FT) with alternate functions UART4_RX and USART3_RX.
80 PC12 bidirectional GPIO PC12 (5 V tolerant, FT) with alternate functions UART5_TX and USART3_CK.
81 PD0 bidirectional GPIO PD0 (5 V tolerant, FT), available by default on LQFP100, with alternate function FSMC_D2.
82 PD1 bidirectional GPIO PD1 (5 V tolerant, FT), available by default on LQFP100, with alternate function FSMC_D3.
83 PD2 bidirectional GPIO PD2 (5 V tolerant, FT) with alternate functions TIM3_ETR and UART5_RX.
84 PD3 bidirectional GPIO PD3 (5 V tolerant, FT) with alternate functions FSMC_CLK and USART2_CTS.
85 PD4 bidirectional GPIO PD4 (5 V tolerant, FT) with alternate functions FSMC_NOE and USART2_RTS.
86 PD5 bidirectional GPIO PD5 (5 V tolerant, FT) with alternate functions FSMC_NWE and USART2_TX.
87 PD6 bidirectional GPIO PD6 (5 V tolerant, FT) with alternate functions FSMC_NWAIT and USART2_RX.
88 PD7 bidirectional GPIO PD7 (5 V tolerant, FT) with alternate functions FSMC_NE1/FSMC_NCE2 and USART2_CK.
89 PB3 bidirectional GPIO PB3 (5 V tolerant, FT); default function JTDO, with alternate functions SPI3_SCK, TIM2_CH2, TRACESWO and SPI1_SCK.
90 PB4 bidirectional GPIO PB4 (5 V tolerant, FT); default function NJTRST, with alternate functions SPI3_MISO, TIM3_CH1 and SPI1_MISO.
91 PB5 bidirectional GPIO PB5 with alternate functions I2C1_SMBA, SPI3_MOSI, TIM3_CH2 and SPI1_MOSI; not marked 5 V tolerant in Table 5.
92 PB6 bidirectional GPIO PB6 (5 V tolerant, FT) with alternate functions I2C1_SCL, TIM4_CH1 and USART1_TX.
93 PB7 bidirectional GPIO PB7 (5 V tolerant, FT) with alternate functions I2C1_SDA, FSMC_NADV, TIM4_CH2 and USART1_RX.
94 BOOT0 input Boot mode pin; the memory aliased at 0x0000 0000 depends on the BOOT pins.
95 PB8 bidirectional GPIO PB8 (5 V tolerant, FT) with alternate functions TIM4_CH3 and I2C1_SCL.
96 PB9 bidirectional GPIO PB9 (5 V tolerant, FT) with alternate functions TIM4_CH4 and I2C1_SDA.
97 PE0 bidirectional GPIO PE0 (5 V tolerant, FT) with alternate functions TIM4_ETR and FSMC_NBL0.
98 PE1 bidirectional GPIO PE1 (5 V tolerant, FT) with alternate function FSMC_NBL1.
99 VSS_3 power_in Digital ground.
100 VDD_3 power_in Digital supply for I/Os and core, 2.0 to 3.6 V application supply.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F101VET6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f101vet6-etched.step / stm32f101vet6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f101vet6.step / stm32f101vet6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (112 pp, sha256 96a9d254df7c3ddd, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF