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Contents

README

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STM32F101R4T6A

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F101R4T6A from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery backup supply for RTC and backup registers, 2.0 to 3.6 V
2 PC13-TAMPER-RTC bidirectional GPIO or RTC tamper/clock input with 3 mA current limit via power switch
3 PC14-OSC32_IN bidirectional 32 kHz oscillator input or GPIO with 3 mA current limit via power switch
4 PC15-OSC32_OUT bidirectional 32 kHz oscillator output or GPIO with 3 mA current limit via power switch
5 PD0-OSC_IN input High-speed external oscillator input (4-16 MHz crystal), configurable as OSC_IN after reset
6 PD1-OSC_OUT output High-speed external oscillator output for crystal feedback
7 NRST input Active low reset input with internal pull-up and Schmitt trigger
8 PC0 bidirectional GPIO or ADC_IN10 analog input, 0 to 3.6 V conversion range
9 PC1 bidirectional GPIO or ADC_IN11 analog input, 0 to 3.6 V conversion range
10 PC2 bidirectional GPIO or ADC_IN12 analog input, 0 to 3.6 V conversion range
11 PC3 bidirectional GPIO or ADC_IN13 analog input, 0 to 3.6 V conversion range
12 VSSA power_in Analog ground supply
13 VDDA power_in Analog supply voltage for ADC and temperature sensor, 2.0 to 3.6 V
14 PA0-WKUP bidirectional GPIO PA0 or wakeup/USART2_CTS/ADC_IN0/TIM2_CH1_ETR with software remapping capability
15 PA1 bidirectional GPIO or USART2_RTS/ADC_IN1/TIM2_CH2 with software remapping capability
16 PA2 bidirectional GPIO or USART2_TX/ADC_IN2/TIM2_CH3 with software remapping capability
17 PA3 bidirectional GPIO or USART2_RX/ADC_IN3/TIM2_CH4 with software remapping capability
18 VSS_4 power_in Ground
19 VDD_4 power_in Main supply voltage, 2.0 to 3.6 V with 100 nF decoupling capacitor recommended
20 PA4 bidirectional GPIO or SPI1_NSS/ADC_IN4/USART2_CK with software remapping capability
21 PA5 bidirectional GPIO or SPI1_SCK/ADC_IN5 with software remapping capability
22 PA6 bidirectional GPIO or SPI1_MISO/ADC_IN6/TIM3_CH1 with software remapping capability
23 PA7 bidirectional GPIO or SPI1_MOSI/ADC_IN7/TIM3_CH2 with software remapping capability
24 PC4 bidirectional GPIO or ADC_IN14 analog input, 0 to 3.6 V conversion range
25 PC5 bidirectional GPIO or ADC_IN15 analog input, 0 to 3.6 V conversion range
26 PB0 bidirectional GPIO or ADC_IN8/TIM3_CH3 with software remapping capability
27 PB1 bidirectional GPIO or ADC_IN9/TIM3_CH4 with software remapping capability
28 PB2 bidirectional GPIO (BOOT1) or 5V tolerant I/O
29 PB10 bidirectional 5V tolerant GPIO with software remappable to TIM2_CH3
30 PB11 bidirectional 5V tolerant GPIO with software remappable to TIM2_CH4
31 VSS_1 power_in Ground
32 VDD_1 power_in Main supply voltage, 2.0 to 3.6 V with 100 nF decoupling capacitor recommended
33 PB12 bidirectional 5V tolerant GPIO
34 PB13 bidirectional 5V tolerant GPIO
35 PB14 bidirectional 5V tolerant GPIO
36 PB15 bidirectional 5V tolerant GPIO
37 PC6 bidirectional 5V tolerant GPIO with software remappable to TIM3_CH1
38 PC7 bidirectional 5V tolerant GPIO with software remappable to TIM3_CH2
39 PC8 bidirectional 5V tolerant GPIO with software remappable to TIM3_CH3
40 PC9 bidirectional 5V tolerant GPIO with software remappable to TIM3_CH4
41 PA8 bidirectional 5V tolerant GPIO or USART1_CK/MCO clock output
42 PA9 bidirectional 5V tolerant GPIO or USART1_TX output with software remapping capability
43 PA10 bidirectional 5V tolerant GPIO or USART1_RX input with software remapping capability
44 PA11 bidirectional 5V tolerant GPIO or USART1_CTS input
45 PA12 bidirectional 5V tolerant GPIO or USART1_RTS output
46 PA13 bidirectional 5V tolerant JTAG TMS/Serial Wire SWDIO debug pin with software remappable to PA13
47 VSS_2 power_in Ground
48 VDD_2 power_in Main supply voltage, 2.0 to 3.6 V with 100 nF decoupling capacitor recommended
49 PA14 bidirectional 5V tolerant JTAG TCK/Serial Wire SWCLK debug pin with software remappable to PA14
50 PA15 bidirectional 5V tolerant JTAG TDI debug pin with software remappable to TIM2_CH1_ETR/PA15/SPI1_NSS
51 PC10 bidirectional 5V tolerant GPIO
52 PC11 bidirectional 5V tolerant GPIO
53 PC12 bidirectional 5V tolerant GPIO
54 PD2 bidirectional 5V tolerant GPIO or TIM3_ETR external trigger input
55 PB3 bidirectional 5V tolerant JTAG TDO debug output with software remappable to TIM2_CH2/PB3/TRACESWO/SPI1_SCK
56 PB4 bidirectional 5V tolerant JTAG NTRST debug pin with software remappable to TIM3_CH1/PB4/SPI1_MISO
57 PB5 bidirectional GPIO or I2C1_SMBA with software remappable to TIM3_CH2/SPI1_MOSI
58 PB6 bidirectional 5V tolerant GPIO or I2C1_SCL with software remappable to USART1_TX
59 PB7 bidirectional 5V tolerant GPIO or I2C1_SDA with software remappable to USART1_RX
60 BOOT0 input Boot configuration pin (0=boot from Flash, 1=boot from system memory)
61 PB8 bidirectional 5V tolerant GPIO with software remappable to I2C1_SCL
62 PB9 bidirectional 5V tolerant GPIO with software remappable to I2C1_SDA
63 VSS_3 power_in Ground
64 VDD_3 power_in Main supply voltage, 2.0 to 3.6 V with 100 nF decoupling capacitor recommended

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32F101R4T6A
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f101r4t6a-etched.step / stm32f101r4t6a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f101r4t6a.step / stm32f101r4t6a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (87 pp, sha256 a0484b8e7d5434bf, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF