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STM32F100VCT6BTR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f100vct6btrfactory-2.0.0extractor-text
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Symbol & Footprint

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Contents

README

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STM32F100VCT6BTR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F100VCT6BTR from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional General-purpose I/O, 5 V tolerant (FT); default function PE2, alternates TRACECK and FSMC_A23.
2 PE3 bidirectional General-purpose I/O, 5 V tolerant (FT); default function PE3, alternates TRACED0 and FSMC_A19.
3 PE4 bidirectional General-purpose I/O, 5 V tolerant (FT); default function PE4, alternates TRACED1 and FSMC_A20.
4 PE5 bidirectional General-purpose I/O, 5 V tolerant (FT); default function PE5, alternates TRACED2 and FSMC_A21.
5 PE6 bidirectional General-purpose I/O, 5 V tolerant (FT); default function PE6, alternates TRACED3 and FSMC_A22.
6 VBAT power_in Backup-domain supply for the RTC and backup registers.
7 PC13 bidirectional PC13 (TAMPER-RTC) is supplied through the power switch, which sinks only 3 mA, so output speed is limited to 2 MHz at 30 pF and it must not drive LEDs or act as a current source.
8 PC14 bidirectional PC14 (OSC32_IN) is supplied through the power switch, so output use is limited to 2 MHz at 30 pF and it must not act as a current source.
9 PC15 bidirectional PC15 (OSC32_OUT) is supplied through the power switch, so output use is limited to 2 MHz at 30 pF and it must not act as a current source.
10 VSS_5 power_in Ground pin of the digital supply domain.
11 VDD_5 power_in Digital supply pin; the application supply and I/Os are specified at 2.0 to 3.6 V.
12 OSC_IN input Oscillator input for the 4-to-24 MHz crystal oscillator.
13 OSC_OUT output Oscillator output for the 4-to-24 MHz crystal oscillator.
14 NRST bidirectional Reset pin (NRST) of the device.
15 PC0 bidirectional Standard I/O (not 5 V tolerant); alternate function ADC_IN10.
16 PC1 bidirectional Standard I/O (not 5 V tolerant); alternate function ADC_IN11.
17 PC2 bidirectional Standard I/O (not 5 V tolerant); alternate function ADC_IN12.
18 PC3 bidirectional Standard I/O (not 5 V tolerant); alternate function ADC_IN13.
19 VSSA power_in Analog ground pin.
20 VREF- power_in Negative reference voltage pin.
21 VREF+ power_in Positive reference voltage pin; the DAC uses VREF+ as its input voltage reference.
22 VDDA power_in Analog supply pin; the temperature sensor conversion range requires 2 V < VDDA < 3.6 V.
23 PA0 bidirectional I/O with WKUP wake-up function; alternates ADC_IN0, USART2_CTS, TIM2_CH1_ETR and TIM5_CH1.
24 PA1 bidirectional I/O; alternates USART2_RTS, ADC_IN1, TIM5_CH2 and TIM2_CH2.
25 PA2 bidirectional I/O; alternates USART2_TX, TIM5_CH3, ADC_IN2, TIM15_CH1 and TIM2_CH3.
26 PA3 bidirectional I/O; alternates USART2_RX, TIM5_CH4, ADC_IN3, TIM2_CH4 and TIM15_CH2.
27 VSS_4 power_in Ground pin of the digital supply domain.
28 VDD_4 power_in Digital supply pin; the application supply and I/Os are specified at 2.0 to 3.6 V.
29 PA4 bidirectional I/O; alternates SPI1_NSS, USART2_CK, DAC_OUT1 and ADC_IN4.
30 PA5 bidirectional I/O; alternates SPI1_SCK, DAC_OUT2 and ADC_IN5.
31 PA6 bidirectional I/O; alternates SPI1_MISO, ADC_IN6, TIM3_CH1, with remap TIM1_BKIN and TIM16_CH1.
32 PA7 bidirectional I/O; alternates SPI1_MOSI, ADC_IN7, TIM3_CH2, with remap TIM1_CH1N and TIM17_CH1.
33 PC4 bidirectional Standard I/O; alternates ADC_IN14 and TIM12_CH1.
34 PC5 bidirectional Standard I/O; alternates ADC_IN15 and TIM12_CH2.
35 PB0 bidirectional Standard I/O; alternates ADC_IN8 and TIM3_CH3, with remap TIM1_CH2N and TIM13_CH1.
36 PB1 bidirectional Standard I/O; alternates ADC_IN9 and TIM3_CH4, with remap TIM1_CH3N and TIM14_CH1.
37 PB2 bidirectional I/O, 5 V tolerant (FT); default function PB2 shared with BOOT1.
38 PE7 bidirectional I/O, 5 V tolerant (FT); default function PE7 with FSMC_D4, remap TIM1_ETR.
39 PE8 bidirectional I/O, 5 V tolerant (FT); default function PE8 with FSMC_D5, remap TIM1_CH1N.
40 PE9 bidirectional I/O, 5 V tolerant (FT); default function PE9 with FSMC_D6, remap TIM1_CH1.
41 PE10 bidirectional I/O, 5 V tolerant (FT); default function PE10 with FSMC_D7, remap TIM1_CH2N.
42 PE11 bidirectional I/O, 5 V tolerant (FT); default function PE11 with FSMC_D8, remap TIM1_CH2.
43 PE12 bidirectional I/O, 5 V tolerant (FT); default function PE12 with FSMC_D9, remap TIM1_CH3N.
44 PE13 bidirectional I/O, 5 V tolerant (FT); default function PE13 with FSMC_D10, remap TIM1_CH3.
45 PE14 bidirectional I/O, 5 V tolerant (FT); default function PE14 with FSMC_D11, remap TIM1_CH4.
46 PE15 bidirectional I/O, 5 V tolerant (FT); default function PE15 with FSMC_D12, remap TIM1_BKIN.
47 PB10 bidirectional I/O, 5 V tolerant (FT); alternates I2C2_SCL and USART3_TX, with remap TIM2_CH3 and HDMI_CEC.
48 PB11 bidirectional I/O, 5 V tolerant (FT); alternates I2C2_SDA and USART3_RX, with remap TIM2_CH4.
49 VSS_1 power_in Ground pin of the digital supply domain.
50 VDD_1 power_in Digital supply pin; the application supply and I/Os are specified at 2.0 to 3.6 V.
51 PB12 bidirectional I/O, 5 V tolerant (FT); alternates SPI2_NSS, I2C2_SMBA, USART3_CK and TIM1_BKIN, with remap TIM12_CH1.
52 PB13 bidirectional I/O, 5 V tolerant (FT); alternates SPI2_SCK, USART3_CTS and TIM1_CH1N, with remap TIM12_CH2.
53 PB14 bidirectional I/O, 5 V tolerant (FT); alternates SPI2_MISO, USART3_RTS, TIM1_CH2N and TIM15_CH1.
54 PB15 bidirectional I/O, 5 V tolerant (FT); alternates SPI2_MOSI, TIM1_CH3N, TIM15_CH1N and TIM15_CH2.
55 PD8 bidirectional I/O, 5 V tolerant (FT); default function PD8 with FSMC_D13 and USART3_TX.
56 PD9 bidirectional I/O, 5 V tolerant (FT); default function PD9 with FSMC_D14 and USART3_RX.
57 PD10 bidirectional I/O, 5 V tolerant (FT); default function PD10 with FSMC_D15 and USART3_CK.
58 PD11 bidirectional I/O, 5 V tolerant (FT); default function PD11 with FSMC_A16 and USART3_CTS.
59 PD12 bidirectional I/O, 5 V tolerant (FT); default function PD12 with FSMC_A17, TIM4_CH1 and USART3_RTS.
60 PD13 bidirectional I/O, 5 V tolerant (FT); default function PD13 with FSMC_A18 and TIM4_CH2.
61 PD14 bidirectional I/O, 5 V tolerant (FT); default function PD14 with FSMC_D0 and TIM4_CH3.
62 PD15 bidirectional I/O, 5 V tolerant (FT); default function PD15 with FSMC_D1 and TIM4_CH4.
63 PC6 bidirectional I/O, 5 V tolerant (FT); alternate function TIM3_CH1.
64 PC7 bidirectional I/O, 5 V tolerant (FT); alternate function TIM3_CH2.
65 PC8 bidirectional I/O, 5 V tolerant (FT); alternates TIM13_CH1 and TIM3_CH3.
66 PC9 bidirectional I/O, 5 V tolerant (FT); alternates TIM14_CH1 and TIM3_CH4.
67 PA8 bidirectional I/O, 5 V tolerant (FT); alternates USART1_CK, TIM1_CH1 and MCO.
68 PA9 bidirectional I/O, 5 V tolerant (FT); alternates USART1_TX, TIM1_CH2 and TIM15_BKIN.
69 PA10 bidirectional I/O, 5 V tolerant (FT); alternates USART1_RX, TIM1_CH3 and TIM17_BKIN.
70 PA11 bidirectional I/O, 5 V tolerant (FT); alternates USART1_CTS and TIM1_CH4.
71 PA12 bidirectional I/O, 5 V tolerant (FT); alternates USART1_RTS and TIM1_ETR.
72 PA13 bidirectional I/O, 5 V tolerant (FT); JTMS-SWDIO debug pin.
73 NC unconnected Not connected.
74 VSS_2 power_in Ground pin of the digital supply domain.
75 VDD_2 power_in Digital supply pin; the application supply and I/Os are specified at 2.0 to 3.6 V.
76 PA14 bidirectional I/O, 5 V tolerant (FT); JTCK-SWCLK debug pin.
77 PA15 bidirectional I/O, 5 V tolerant (FT); JTDI, with SPI3_NSS and TIM2_CH1_ETR / SPI1_NSS alternates.
78 PC10 bidirectional I/O, 5 V tolerant (FT); alternates UART4_TX and USART3_TX.
79 PC11 bidirectional I/O, 5 V tolerant (FT); alternates UART4_RX and USART3_RX.
80 PC12 bidirectional I/O, 5 V tolerant (FT); alternates UART5_TX and USART3_CK.
81 PD0 bidirectional I/O, 5 V tolerant (FT); default function PD0 with FSMC_D2, available by default on LQFP100.
82 PD1 bidirectional I/O, 5 V tolerant (FT); default function PD1 with FSMC_D3, available by default on LQFP100.
83 PD2 bidirectional I/O, 5 V tolerant (FT); alternates TIM3_ETR and UART5_RX.
84 PD3 bidirectional I/O, 5 V tolerant (FT); default function PD3 with FSMC_CLK and USART2_CTS.
85 PD4 bidirectional I/O, 5 V tolerant (FT); default function PD4 with FSMC_NOE and USART2_RTS.
86 PD5 bidirectional I/O, 5 V tolerant (FT); default function PD5 with FSMC_NWE and USART2_TX.
87 PD6 bidirectional I/O, 5 V tolerant (FT); default function PD6 with FSMC_NWAIT and USART2_RX.
88 PD7 bidirectional I/O, 5 V tolerant (FT); default function PD7 with FSMC_NE1 and USART2_CK.
89 PB3 bidirectional I/O, 5 V tolerant (FT); JTDO/TRACESWO debug function, with SPI3_SCK, TIM2_CH2 and SPI1_SCK alternates.
90 PB4 bidirectional I/O, 5 V tolerant (FT); NJTRST debug function, with SPI3_MISO, TIM3_CH1 and SPI1_MISO alternates.
91 PB5 bidirectional I/O (not 5 V tolerant per table); alternates I2C1_SMBA, SPI3_MOSI, TIM16_BKIN, TIM3_CH2 and SPI1_MOSI.
92 PB6 bidirectional I/O, 5 V tolerant (FT); alternates I2C1_SCL, TIM4_CH1, TIM16_CH1N and USART1_TX.
93 PB7 bidirectional I/O, 5 V tolerant (FT); alternates I2C1_SDA, FSMC_NADV, TIM4_CH2, TIM17_CH1N and USART1_RX.
94 BOOT0 input Boot mode selection input (BOOT0).
95 PB8 bidirectional I/O, 5 V tolerant (FT); alternates TIM4_CH3, TIM16_CH1, HDMI_CEC and I2C1_SCL.
96 PB9 bidirectional I/O, 5 V tolerant (FT); alternates TIM4_CH4, TIM17_CH1 and I2C1_SDA.
97 PE0 bidirectional I/O, 5 V tolerant (FT); alternates TIM4_ETR and FSMC_NBL0.
98 PE1 bidirectional I/O, 5 V tolerant (FT); alternate function FSMC_NBL1.
99 VSS_3 power_in Ground pin of the digital supply domain.
100 VDD_3 power_in Digital supply pin; the application supply and I/Os are specified at 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F100VCT6BTR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f100vct6btr-etched.step / stm32f100vct6btr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f100vct6btr.step / stm32f100vct6btr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (107 pp, sha256 37ac4e5d049f3b5d, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF