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STM32F100VBT6BTR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f100vbt6btrfactory-2.0.0extractor-text
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Contents

README

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STM32F100VBT6BTR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F100VBT6BTR from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant (FT) general-purpose I/O PE2, with TRACECLK as alternate function.
2 PE3 bidirectional 5 V-tolerant (FT) general-purpose I/O PE3, with TRACED0 as alternate function.
3 PE4 bidirectional 5 V-tolerant (FT) general-purpose I/O PE4, with TRACED1 as alternate function.
4 PE5 bidirectional 5 V-tolerant (FT) general-purpose I/O PE5, with TRACED2 as alternate function.
5 PE6 bidirectional 5 V-tolerant (FT) general-purpose I/O PE6, with TRACED3 as alternate function.
6 VBAT power_in Backup-domain supply for the RTC and backup registers.
7 PC13-TAMPER-RTC bidirectional I/O PC13 (not 5 V tolerant) with TAMPER-RTC function; supplied through the power switch, which sinks only 3 mA, so it must not exceed 2 MHz with a 30 pF load and must not be used as a current source such as an LED driver.
8 PC14-OSC32_IN bidirectional I/O PC14 (not 5 V tolerant) with OSC32_IN function; supplied through the power switch (3 mA sink limit), so output use is limited to 2 MHz, 30 pF load and no current sourcing.
9 PC15-OSC32_OUT bidirectional I/O PC15 (not 5 V tolerant) with OSC32_OUT function; supplied through the power switch (3 mA sink limit), so output use is limited to 2 MHz, 30 pF load and no current sourcing.
10 VSS_5 power_in Digital ground pin.
11 VDD_5 power_in Digital supply pin for the 2.0 to 3.6 V application supply and I/Os.
12 OSC_IN input Input of the 4-24 MHz crystal oscillator; after reset this pin is OSC_IN, and PD0 can be remapped onto it.
13 OSC_OUT output Output of the 4-24 MHz crystal oscillator; after reset this pin is OSC_OUT, and PD1 can be remapped onto it.
14 NRST bidirectional Device reset pin NRST (I/O in the pin table).
15 PC0 bidirectional I/O PC0 (not 5 V tolerant) with ADC1_IN10 analog input.
16 PC1 bidirectional I/O PC1 (not 5 V tolerant) with ADC1_IN11 analog input.
17 PC2 bidirectional I/O PC2 (not 5 V tolerant) with ADC1_IN12 analog input.
18 PC3 bidirectional I/O PC3 (not 5 V tolerant) with ADC1_IN13 analog input.
19 VSSA power_in Analog ground pin for the ADC and analog blocks.
20 VREF- power_in Negative reference voltage pin for the ADC; it can be internally connected to VSSA depending on the package.
21 VREF+ power_in Positive reference voltage pin for the ADC and DAC; it can be internally connected to VDDA depending on the package.
22 VDDA power_in Analog supply pin for the ADC and analog blocks.
23 PA0-WKUP bidirectional 5 V-tolerant (FT) I/O PA0 with WKUP wake-up function; alternates USART2_CTS, ADC1_IN0 and TIM2_CH1_ETR.
24 PA1 bidirectional 5 V-tolerant (FT) I/O PA1; alternates USART2_RTS, ADC1_IN1 and TIM2_CH2.
25 PA2 bidirectional 5 V-tolerant (FT) I/O PA2; alternates USART2_TX, ADC1_IN2, TIM2_CH3 and TIM15_CH1.
26 PA3 bidirectional 5 V-tolerant (FT) I/O PA3; alternates USART2_RX, ADC1_IN3, TIM2_CH4 and TIM15_CH2.
27 VSS_4 power_in Digital ground pin.
28 VDD_4 power_in Digital supply pin for the 2.0 to 3.6 V application supply and I/Os.
29 PA4 bidirectional 5 V-tolerant (FT) I/O PA4; alternates SPI1_NSS, ADC1_IN4, USART2_CK and DAC1_OUT.
30 PA5 bidirectional 5 V-tolerant (FT) I/O PA5; alternates SPI1_SCK, ADC1_IN5 and DAC2_OUT.
31 PA6 bidirectional 5 V-tolerant (FT) I/O PA6; alternates SPI1_MISO, ADC1_IN6 and TIM3_CH1, with TIM1_BKIN and TIM16_CH1 as remap options.
32 PA7 bidirectional 5 V-tolerant (FT) I/O PA7; alternates SPI1_MOSI, ADC1_IN7 and TIM3_CH2, with TIM1_CH1N and TIM17_CH1 as remap options.
33 PC4 bidirectional I/O PC4 (not 5 V tolerant) with ADC1_IN14 analog input.
34 PC5 bidirectional I/O PC5 (not 5 V tolerant) with ADC1_IN15 analog input.
35 PB0 bidirectional I/O PB0 (not 5 V tolerant) with ADC1_IN8 and TIM3_CH3; TIM1_CH2N as remap option.
36 PB1 bidirectional I/O PB1 (not 5 V tolerant) with ADC1_IN9 and TIM3_CH4; TIM1_CH3N as remap option.
37 PB2 bidirectional 5 V-tolerant (FT) I/O PB2, shared with the BOOT1 function.
38 PE7 bidirectional 5 V-tolerant (FT) I/O PE7 with TIM1_ETR as remap option.
39 PE8 bidirectional 5 V-tolerant (FT) I/O PE8 with TIM1_CH1N as remap option.
40 PE9 bidirectional 5 V-tolerant (FT) I/O PE9 with TIM1_CH1 as remap option.
41 PE10 bidirectional 5 V-tolerant (FT) I/O PE10 with TIM1_CH2N as remap option.
42 PE11 bidirectional 5 V-tolerant (FT) I/O PE11 with TIM1_CH2 as remap option.
43 PE12 bidirectional 5 V-tolerant (FT) I/O PE12 with TIM1_CH3N as remap option.
44 PE13 bidirectional 5 V-tolerant (FT) I/O PE13 with TIM1_CH3 as remap option.
45 PE14 bidirectional 5 V-tolerant (FT) I/O PE14 with TIM1_CH4 as remap option.
46 PE15 bidirectional 5 V-tolerant (FT) I/O PE15 with TIM1_BKIN as remap option.
47 PB10 bidirectional 5 V-tolerant (FT) I/O PB10; alternates I2C2_SCL, USART3_TX, TIM2_CH3 and HDMI_CEC.
48 PB11 bidirectional 5 V-tolerant (FT) I/O PB11; alternates I2C2_SDA, USART3_RX and TIM2_CH4.
49 VSS_1 power_in Digital ground pin.
50 VDD_1 power_in Digital supply pin for the 2.0 to 3.6 V application supply and I/Os.
51 PB12 bidirectional 5 V-tolerant (FT) I/O PB12; alternates SPI2_NSS, I2C2_SMBA, TIM1_BKIN and USART3_CK.
52 PB13 bidirectional 5 V-tolerant (FT) I/O PB13; alternates SPI2_SCK, TIM1_CH1N and USART3_CTS.
53 PB14 bidirectional 5 V-tolerant (FT) I/O PB14; alternates SPI2_MISO, TIM1_CH2N and USART3_RTS, with TIM15_CH1 as remap option.
54 PB15 bidirectional 5 V-tolerant (FT) I/O PB15; alternates SPI2_MOSI, TIM1_CH3N and TIM15_CH1N, with TIM15_CH2 as remap option.
55 PD8 bidirectional 5 V-tolerant (FT) I/O PD8 with USART3_TX as remap option.
56 PD9 bidirectional 5 V-tolerant (FT) I/O PD9 with USART3_RX as remap option.
57 PD10 bidirectional 5 V-tolerant (FT) I/O PD10 with USART3_CK as remap option.
58 PD11 bidirectional 5 V-tolerant (FT) I/O PD11 with USART3_CTS as remap option.
59 PD12 bidirectional 5 V-tolerant (FT) I/O PD12 with TIM4_CH1 and USART3_RTS as remap options.
60 PD13 bidirectional 5 V-tolerant (FT) I/O PD13 with TIM4_CH2 as remap option.
61 PD14 bidirectional 5 V-tolerant (FT) I/O PD14 with TIM4_CH3 as remap option.
62 PD15 bidirectional 5 V-tolerant (FT) I/O PD15 with TIM4_CH4 as remap option.
63 PC6 bidirectional 5 V-tolerant (FT) I/O PC6 with TIM3_CH1 as remap option.
64 PC7 bidirectional 5 V-tolerant (FT) I/O PC7 with TIM3_CH2 as remap option.
65 PC8 bidirectional 5 V-tolerant (FT) I/O PC8 with TIM3_CH3 as remap option.
66 PC9 bidirectional 5 V-tolerant (FT) I/O PC9 with TIM3_CH4 as remap option.
67 PA8 bidirectional 5 V-tolerant (FT) I/O PA8; alternates USART1_CK, MCO and TIM1_CH1.
68 PA9 bidirectional 5 V-tolerant (FT) I/O PA9; alternates USART1_TX, TIM1_CH2 and TIM15_BKIN.
69 PA10 bidirectional 5 V-tolerant (FT) I/O PA10; alternates USART1_RX, TIM1_CH3 and TIM17_BKIN.
70 PA11 bidirectional 5 V-tolerant (FT) I/O PA11; alternates USART1_CTS and TIM1_CH4.
71 PA12 bidirectional 5 V-tolerant (FT) I/O PA12; alternates USART1_RTS and TIM1_ETR.
72 PA13 bidirectional 5 V-tolerant (FT) I/O PA13; default function JTMS-SWDIO (debug).
73 NC unconnected Not connected.
74 VSS_2 power_in Digital ground pin.
75 VDD_2 power_in Digital supply pin for the 2.0 to 3.6 V application supply and I/Os.
76 PA14 bidirectional 5 V-tolerant (FT) I/O PA14; default function JTCK/SWCLK (debug).
77 PA15 bidirectional 5 V-tolerant (FT) I/O PA15; default function JTDI, with TIM2_CH1_ETR and SPI1_NSS as remap options.
78 PC10 bidirectional 5 V-tolerant (FT) I/O PC10 with USART3_TX as remap option.
79 PC11 bidirectional 5 V-tolerant (FT) I/O PC11 with USART3_RX as remap option.
80 PC12 bidirectional 5 V-tolerant (FT) I/O PC12 with USART3_CK as remap option.
81 PD0 bidirectional 5 V-tolerant (FT) general-purpose I/O PD0; no alternate function is listed for this pin in Table 4.
82 PD1 bidirectional 5 V-tolerant (FT) general-purpose I/O PD1; no alternate function is listed for this pin in Table 4.
83 PD2 bidirectional 5 V-tolerant (FT) I/O PD2 with TIM3_ETR as alternate function.
84 PD3 bidirectional 5 V-tolerant (FT) I/O PD3 with USART2_CTS as remap option.
85 PD4 bidirectional 5 V-tolerant (FT) I/O PD4 with USART2_RTS as remap option.
86 PD5 bidirectional 5 V-tolerant (FT) I/O PD5 with USART2_TX as remap option.
87 PD6 bidirectional 5 V-tolerant (FT) I/O PD6 with USART2_RX as remap option.
88 PD7 bidirectional 5 V-tolerant (FT) I/O PD7 with USART2_CK as remap option.
89 PB3 bidirectional 5 V-tolerant (FT) I/O PB3; default function JTDO, with TIM2_CH2, TRACESWO, SPI1_SCK and PB3 as other functions.
90 PB4 bidirectional 5 V-tolerant (FT) I/O PB4; default function NJTRST, with TIM3_CH1 and SPI1_MISO as remap options.
91 PB5 bidirectional I/O PB5 (not 5 V tolerant) with I2C1_SMBA and TIM16_BKIN; TIM3_CH2 and SPI1_MOSI as remap options.
92 PB6 bidirectional 5 V-tolerant (FT) I/O PB6; alternates I2C1_SCL and TIM4_CH1, with TIM16_CH1N and USART1_TX as remap options.
93 PB7 bidirectional 5 V-tolerant (FT) I/O PB7; alternates I2C1_SDA, TIM17_CH1N and TIM4_CH2, with USART1_RX as remap option.
94 BOOT0 input Boot mode selection input BOOT0.
95 PB8 bidirectional 5 V-tolerant (FT) I/O PB8; alternates TIM4_CH3, TIM16_CH1, CEC and I2C1_SCL.
96 PB9 bidirectional 5 V-tolerant (FT) I/O PB9; alternates TIM4_CH4, TIM17_CH1 and I2C1_SDA.
97 PE0 bidirectional 5 V-tolerant (FT) I/O PE0 with TIM4_ETR as alternate function.
98 PE1 bidirectional 5 V-tolerant (FT) general-purpose I/O PE1; no alternate function is listed for this pin in Table 4.
99 VSS_3 power_in Digital ground pin.
100 VDD_3 power_in Digital supply pin for the 2.0 to 3.6 V application supply and I/Os.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F100VBT6BTR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f100vbt6btr-etched.step / stm32f100vbt6btr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f100vbt6btr.step / stm32f100vbt6btr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (96 pp, sha256 360e3be010cabad4, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF