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STM32F100C8T7B

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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Contents

README

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STM32F100C8T7B

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32F100C8T7B from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply for the RTC and backup registers, which the datasheet lists as a VBAT supply input.
2 PC13-TAMPER-RTC bidirectional GPIO PC13 also used as TAMPER-RTC; it is supplied through the power switch, which sinks only about 3 mA, so output use is limited to 2 MHz with a 30 pF load and it must not source current such as driving an LED.
3 PC14-OSC32_IN bidirectional GPIO PC14 also used as the 32 kHz oscillator input OSC32_IN, with the same power-switch limits as PC13 (2 MHz max at 30 pF, no current sourcing).
4 PC15-OSC32_OUT bidirectional GPIO PC15 also used as the 32 kHz oscillator output OSC32_OUT, with the same power-switch limits as PC13 (2 MHz max at 30 pF, no current sourcing).
5 OSC_IN input Input to the 4-to-24 MHz crystal oscillator; it is configured as OSC_IN after reset and its function can be remapped to PD0 by software.
6 OSC_OUT output Output of the 4-to-24 MHz crystal oscillator; it is configured as OSC_OUT after reset and its function can be remapped to PD1 by software.
7 NRST bidirectional Device reset pin, listed as an I/O with no alternate function in Table 4; its electrical limits are in section 5.3.14, which is not in the provided text.
8 VSSA power_in Analog ground for the ADC, DAC and analog circuitry; all voltages in the datasheet are referenced to VSS.
9 VDDA power_in Analog supply for the ADC and DAC, with the ADC VDDA range given as 2.4 to 3.6 V in Table 42.
10 PA0-WKUP bidirectional Standard I/O (not 5 V tolerant) that serves as the WKUP wakeup input and also as USART2_CTS, ADC1_IN0 and TIM2_CH1_ETR.
11 PA1 bidirectional Standard I/O (not 5 V tolerant) with alternate functions USART2_RTS, ADC1_IN1 and TIM2_CH2.
12 PA2 bidirectional Standard I/O (not 5 V tolerant) with alternate functions USART2_TX, ADC1_IN2, TIM2_CH3 and TIM15_CH1.
13 PA3 bidirectional Standard I/O (not 5 V tolerant) with alternate functions USART2_RX, ADC1_IN3, TIM2_CH4 and TIM15_CH2.
14 PA4 bidirectional Standard I/O (not 5 V tolerant) with alternate functions SPI1_NSS, ADC1_IN4, USART2_CK and DAC1_OUT.
15 PA5 bidirectional Standard I/O (not 5 V tolerant) with alternate functions SPI1_SCK, ADC1_IN5 and DAC2_OUT.
16 PA6 bidirectional Standard I/O (not 5 V tolerant) with alternate functions SPI1_MISO, ADC1_IN6 and TIM3_CH1, with TIM1_BKIN and TIM16_CH1 as remap options.
17 PA7 bidirectional Standard I/O (not 5 V tolerant) with alternate functions SPI1_MOSI, ADC1_IN7 and TIM3_CH2, with TIM1_CH1N and TIM17_CH1 as remap options.
18 PB0 bidirectional Standard I/O (not 5 V tolerant) with alternate functions ADC1_IN8 and TIM3_CH3, with TIM1_CH2N as remap option.
19 PB1 bidirectional Standard I/O (not 5 V tolerant) with alternate functions ADC1_IN9 and TIM3_CH4, with TIM1_CH3N as remap option.
20 PB2/BOOT1 bidirectional 5 V-tolerant I/O (FT) that also serves as the BOOT1 boot-mode pin.
21 PB10 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2C2_SCL, USART3_TX, TIM2_CH3 and HDMI_CEC.
22 PB11 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2C2_SDA, USART3_RX and TIM2_CH4.
23 VSS_1 power_in Digital ground pin for the device core and I/O.
24 VDD_1 power_in Digital supply pin; the application supply and I/O range is 2.0 to 3.6 V.
25 PB12 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_NSS, I2C2_SMBA, TIM1_BKIN and USART3_CK.
26 PB13 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_SCK, TIM1_CH1N and USART3_CTS.
27 PB14 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_MISO, TIM1_CH2N, USART3_RTS and TIM15_CH1.
28 PB15 bidirectional 5 V-tolerant I/O (FT) with alternate functions SPI2_MOSI, TIM1_CH3N and TIM15_CH1N, with TIM15_CH2 as remap option.
29 PA8 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART1_CK, MCO and TIM1_CH1.
30 PA9 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART1_TX, TIM1_CH2 and TIM15_BKIN.
31 PA10 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART1_RX, TIM1_CH3 and TIM17_BKIN.
32 PA11 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART1_CTS and TIM1_CH4.
33 PA12 bidirectional 5 V-tolerant I/O (FT) with alternate functions USART1_RTS and TIM1_ETR.
34 PA13 bidirectional 5 V-tolerant I/O (FT) whose default function is JTMS-SWDIO for serial-wire debug.
35 VSS_2 power_in Digital ground pin for the device core and I/O.
36 VDD_2 power_in Digital supply pin; the application supply and I/O range is 2.0 to 3.6 V.
37 PA14 bidirectional 5 V-tolerant I/O (FT) whose default function is JTCK-SWCLK for serial-wire debug.
38 PA15 bidirectional 5 V-tolerant I/O (FT) whose default function is JTDI, with TIM2_CH1_ETR and SPI1_NSS listed as remap options.
39 PB3 bidirectional 5 V-tolerant I/O (FT) whose default function is JTDO, with TIM2_CH2, TRACESWO and SPI1_SCK as alternate or remap functions.
40 PB4 bidirectional 5 V-tolerant I/O (FT) whose default function is NJTRST, with TIM3_CH1 and SPI1_MISO as alternate or remap functions.
41 PB5 bidirectional Standard I/O (not 5 V tolerant) with alternate functions I2C1_SMBA and TIM16_BKIN, with TIM3_CH2 and SPI1_MOSI as remap options.
42 PB6 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2C1_SCL, TIM4_CH1, TIM16_CH1N and USART1_TX.
43 PB7 bidirectional 5 V-tolerant I/O (FT) with alternate functions I2C1_SDA, TIM17_CH1N, TIM4_CH2 and USART1_RX.
44 BOOT0 input Boot-mode selection input listed as type I with no alternate function in Table 4.
45 PB8 bidirectional 5 V-tolerant I/O (FT) with alternate functions TIM4_CH3, TIM16_CH1, CEC and I2C1_SCL.
46 PB9 bidirectional 5 V-tolerant I/O (FT) with alternate functions TIM4_CH4, TIM17_CH1 and I2C1_SDA.
47 VSS_3 power_in Digital ground pin for the device core and I/O.
48 VDD_3 power_in Digital supply pin; the application supply and I/O range is 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: STM32F100C8T7B
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f100c8t7b-etched.step / stm32f100c8t7b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f100c8t7b.step / stm32f100c8t7b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (96 pp, sha256 360e3be010cabad4, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF