component

STM32F072RBT6

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f072rbt6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

STM32F072RBT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F072RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply pin for RTC, external 32.768 kHz oscillator and backup registers, 1.65 V to 3.6 V.
2 PC13 bidirectional GPIO supplied through the internal power switch (limited to 2 MHz/30 pF in output mode, not usable as current source) with alternate functions WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT.
3 PC14-OSC32_IN (PC14) bidirectional GPIO supplied through the power switch, alternatively usable as OSC32_IN input for the 32.768 kHz LSE crystal oscillator.
4 PC15-OSC32_OUT (PC15) bidirectional GPIO supplied through the power switch, alternatively usable as OSC32_OUT for the 32.768 kHz LSE crystal oscillator.
5 PF0-OSC_IN (PF0) bidirectional 5 V-tolerant GPIO with CRS_SYNC alternate function, alternatively usable as OSC_IN for the 4-32 MHz HSE oscillator.
6 PF1-OSC_OUT (PF1) bidirectional 5 V-tolerant GPIO, alternatively usable as OSC_OUT for the 4-32 MHz HSE oscillator.
7 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor; active-low device reset input / internal reset output.
8 PC0 bidirectional 3.3 V ADC-tolerant GPIO with additional function ADC_IN10 and EVENTOUT alternate function.
9 PC1 bidirectional 3.3 V ADC-tolerant GPIO with additional function ADC_IN11 and EVENTOUT alternate function.
10 PC2 bidirectional 3.3 V ADC-tolerant GPIO with additional function ADC_IN12, alternate functions SPI2_MISO/I2S2_MCK and EVENTOUT.
11 PC3 bidirectional 3.3 V ADC-tolerant GPIO with additional function ADC_IN13, alternate functions SPI2_MOSI/I2S2_SD and EVENTOUT.
12 VSSA power_in Analog ground reference for the ADC, DAC, reset block, RC oscillators and PLL.
13 VDDA power_in External analog supply pin, from VDD to 3.6 V (minimum 2.4 V required when ADC or DAC is used).
14 PA0 bidirectional 3.3 V ADC-tolerant GPIO with additional functions ADC_IN0, WKUP1, RTC_TAMP2, COMP1_INM6, and alternate functions USART2_CTS, TIM2_CH1_ETR, COMP1_OUT, TSC_G1_IO1, USART4_TX.
15 PA1 bidirectional 3.3 V ADC-tolerant GPIO with additional functions ADC_IN1 and COMP1_INP, and alternate functions USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX, EVENTOUT.
16 PA2 bidirectional 3.3 V ADC-tolerant GPIO with additional functions ADC_IN2, COMP2_INM6, WKUP4, and alternate functions USART2_TX, COMP2_OUT, TIM2_CH3, TIM15_CH1, TSC_G1_IO3.
17 PA3 bidirectional 3.3 V ADC-tolerant GPIO with additional functions ADC_IN3 and COMP2_INP, and alternate functions USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4.
18 VSS power_in Digital ground pin.
19 VDD power_in Digital power supply and internal regulator input, 2.0 V to 3.6 V.
20 PA4 bidirectional 3.3 V ADC-tolerant GPIO with additional functions ADC_IN4, DAC_OUT1, COMP1_INM4, COMP2_INM4, and alternate functions SPI1_NSS/I2S1_WS, USART2_CK, TIM14_CH1, TSC_G2_IO1.
21 PA5 bidirectional 3.3 V ADC-tolerant GPIO with additional functions ADC_IN5, DAC_OUT2, COMP1_INM5, COMP2_INM5, and alternate functions SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2.
22 PA6 bidirectional 3.3 V ADC-tolerant GPIO with additional function ADC_IN6, and alternate functions SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT, USART3_CTS.
23 PA7 bidirectional 3.3 V ADC-tolerant GPIO with additional function ADC_IN7, and alternate functions SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT.
24 PC4 bidirectional 3.3 V ADC-tolerant GPIO with additional function ADC_IN14, and alternate functions EVENTOUT, USART3_TX.
25 PC5 bidirectional 3.3 V ADC-tolerant GPIO with additional functions ADC_IN15 and WKUP5, and alternate functions TSC_G3_IO1, USART3_RX.
26 PB0 bidirectional 3.3 V ADC-tolerant GPIO with additional function ADC_IN8, and alternate functions TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, USART3_CK.
27 PB1 bidirectional 3.3 V ADC-tolerant GPIO with additional function ADC_IN9, and alternate functions TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3.
28 PB2 bidirectional 5 V-tolerant GPIO with alternate function TSC_G3_IO4.
29 PB10 bidirectional 5 V-tolerant GPIO with alternate functions SPI2_SCK/I2S2_CK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC, TIM2_CH3.
30 PB11 bidirectional 5 V-tolerant GPIO with alternate functions USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1, I2C2_SDA.
31 VSS power_in Digital ground pin.
32 VDD power_in Digital power supply, 2.0 V to 3.6 V.
33 PB12 bidirectional 5 V-tolerant GPIO with alternate functions TIM1_BKIN, TIM15_BKIN, SPI2_NSS/I2S2_WS, USART3_CK, TSC_G6_IO2, EVENTOUT.
34 PB13 bidirectional 5 V-tolerant, FM+ capable GPIO with alternate functions SPI2_SCK/I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N, TSC_G6_IO3.
35 PB14 bidirectional 5 V-tolerant, FM+ capable GPIO with alternate functions SPI2_MISO/I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4.
36 PB15 bidirectional 5 V-tolerant GPIO with additional functions WKUP7, RTC_REFIN, and alternate functions SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2.
37 PC6 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate function TIM3_CH1.
38 PC7 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate function TIM3_CH2.
39 PC8 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate function TIM3_CH3.
40 PC9 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate function TIM3_CH4.
41 PA8 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate functions MCO, USART1_CK, TIM1_CH1, EVENTOUT, CRS_SYNC.
42 PA9 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate functions TIM15_BKIN, USART1_TX, TIM1_CH2, TSC_G4_IO1.
43 PA10 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate functions TIM17_BKIN, USART1_RX, TIM1_CH3, TSC_G4_IO2.
44 PA11 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with additional function USB_DM, and alternate functions EVENTOUT, USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, CAN_RX.
45 PA12 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with additional function USB_DP, and alternate functions EVENTOUT, USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, CAN_TX.
46 PA13 bidirectional 5 V-tolerant GPIO supplied by VDDIO2, configured after reset as SWDIO with internal pull-up activated; alternate functions IR_OUT, USB_NOE.
47 VSS power_in Digital ground pin.
48 VDDIO2 power_in External digital power supply for the marked 5 V-tolerant I/Os, 1.65 V to 3.6 V, independent of VDD/VDDA but must not be supplied without a valid VDD.
49 PA14 bidirectional 5 V-tolerant GPIO supplied by VDDIO2, configured after reset as SWCLK with internal pull-down activated; alternate function USART2_TX.
50 PA15 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate functions SPI1_NSS/I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR, EVENTOUT.
51 PC10 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate functions USART3_TX, USART4_TX.
52 PC11 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate functions USART3_RX, USART4_RX.
53 PC12 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate functions USART3_CK, USART4_CK.
54 PD2 bidirectional 5 V-tolerant GPIO supplied by VDDIO2 with alternate functions USART3_RTS, TIM3_ETR.
55 PB3 bidirectional 5 V-tolerant GPIO with alternate functions SPI1_SCK/I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT.
56 PB4 bidirectional 5 V-tolerant GPIO with alternate functions SPI1_MISO/I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT.
57 PB5 bidirectional 5 V-tolerant GPIO with additional function WKUP6, and alternate functions SPI1_MOSI/I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2.
58 PB6 bidirectional 5 V-tolerant, FM+ capable GPIO used for USART1 bootloader entry, with alternate functions I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3.
59 PB7 bidirectional 5 V-tolerant, FM+ capable GPIO used for I2C bootloader entry, with alternate functions I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4.
60 BOOT0 input Dedicated boot memory selection pin, sampled at reset (input range 0 to 9.0 V absolute maximum) to select the boot source.
61 PB8 bidirectional 5 V-tolerant, FM+ capable GPIO with alternate functions I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC, CAN_RX.
62 PB9 bidirectional 5 V-tolerant, FM+ capable GPIO with alternate functions SPI2_NSS/I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT, CAN_TX.
63 VSS power_in Digital ground pin.
64 VDD power_in Digital power supply, 2.0 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32F072RBT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f072rbt6-etched.step / stm32f072rbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f072rbt6.step / stm32f072rbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (135 pp, sha256 026abcc24a1196f2, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-5 (text+vision), consensus claude-opus-4-8 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF