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STM32F072CBU7

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F072CBU7

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)

STM32F072CBU7 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply for the RTC, the 32 kHz oscillator and backup registers, 1.65 to 3.6 V, used when VDD is not present.
2 PC13 bidirectional Standard 3.3 V I/O supplied through the power switch, limited to 3 mA sink, so output speed should not exceed 2 MHz at 30 pF and it must not drive current sources; also WKUP2, RTC_TAMP1, RTC_TS and RTC_OUT.
3 PC14-OSC32_IN bidirectional Standard 3.3 V I/O on the backup power switch with the same 3 mA and 2 MHz / 30 pF output limits as PC13, and the alternate function OSC32_IN (32.768 kHz oscillator input).
4 PC15-OSC32_OUT bidirectional Standard 3.3 V I/O on the backup power switch with the same 3 mA and 2 MHz / 30 pF output limits as PC13, and the alternate function OSC32_OUT (32.768 kHz oscillator output).
5 PF0-OSC_IN bidirectional 5 V-tolerant I/O with alternate functions CRS_SYNC and OSC_IN (external 4 to 32 MHz crystal oscillator input).
6 PF1-OSC_OUT bidirectional 5 V-tolerant I/O with the alternate function OSC_OUT (external 4 to 32 MHz crystal oscillator output).
7 NRST bidirectional Device reset input and internal reset output, active low, with an embedded weak pull-up resistor.
8 VSSA power_in Analog ground.
9 VDDA power_in Analog power supply from VDD to 3.6 V, which must always be greater than or equal to VDD and be established first; minimum 2.4 V when the ADC or DAC is used.
10 PA0 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN0) with alternate functions USART2_CTS, TIM2_CH1_ETR, COMP1_OUT, TSC_G1_IO1 and USART4_TX, and additional functions WKUP1, RTC_TAMP2 and COMP1_INM6.
11 PA1 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN1) with alternate functions USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX and EVENTOUT, and additional function COMP1_INP.
12 PA2 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN2) with alternate functions USART2_TX, COMP2_OUT, TIM2_CH3, TIM15_CH1 and TSC_G1_IO3, and additional functions COMP2_INM6 and WKUP4.
13 PA3 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN3) with alternate functions USART2_RX, TIM2_CH4, TIM15_CH2 and TSC_G1_IO4, and additional function COMP2_INP.
14 PA4 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN4) with alternate functions SPI1_NSS, I2S1_WS, USART2_CK, TIM14_CH1 and TSC_G2_IO1, and additional functions COMP1_INM4, COMP2_INM4 and DAC_OUT1.
15 PA5 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN5) with alternate functions SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR and TSC_G2_IO2, and additional functions COMP1_INM5, COMP2_INM5 and DAC_OUT2.
16 PA6 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN6) with alternate functions SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT and USART3_CTS.
17 PA7 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN7) with alternate functions SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4 and EVENTOUT.
18 PB0 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN8) with alternate functions TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT and USART3_CK.
19 PB1 bidirectional 3.3 V-tolerant I/O directly connected to ADC (ADC_IN9) with alternate functions TIM14_CH1, TIM3_CH4, USART3_RTS, TIM1_CH3N and TSC_G3_IO3.
20 PB2 bidirectional 5 V-tolerant I/O with the alternate function TSC_G3_IO4 (capacitive sensing).
21 PB10 bidirectional 5 V-tolerant I/O with alternate functions SPI2_SCK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC and TIM2_CH3.
22 PB11 bidirectional 5 V-tolerant I/O with alternate functions USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1 and I2C2_SDA.
23 VSS power_in Ground.
24 VDD power_in Digital power supply, 2.0 to 3.6 V, which also supplies the internal regulator.
25 PB12 bidirectional 5 V-tolerant I/O with alternate functions TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK, TSC_G6_IO2 and EVENTOUT.
26 PB13 bidirectional 5 V-tolerant I/O, FM+ capable, with alternate functions SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N and TSC_G6_IO3.
27 PB14 bidirectional 5 V-tolerant I/O, FM+ capable, with alternate functions SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1 and TSC_G6_IO4.
28 PB15 bidirectional 5 V-tolerant I/O with alternate functions SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N and TIM15_CH2, and additional functions WKUP7 and RTC_REFIN.
29 PA8 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate functions USART1_CK, TIM1_CH1, EVENTOUT, MCO and CRS_SYNC.
30 PA9 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate functions USART1_TX, TIM1_CH2, TIM15_BKIN and TSC_G4_IO1.
31 PA10 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate functions USART1_RX, TIM1_CH3, TIM17_BKIN and TSC_G4_IO2.
32 PA11 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate functions CAN_RX, USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3 and EVENTOUT, and additional function USB_DM.
33 PA12 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate functions CAN_TX, USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4 and EVENTOUT, and additional function USB_DP.
34 PA13 bidirectional 5 V-tolerant I/O supplied by VDDIO2 that after reset is the SWDIO alternate function with internal pull-up enabled, also IR_OUT and USB_NOE.
35 VSS power_in Ground.
36 VDDIO2 power_in Digital power supply for the marked I/Os, 1.65 to 3.6 V, independent from VDD but not to be provided without a valid VDD supply.
37 PA14 bidirectional 5 V-tolerant I/O supplied by VDDIO2 that after reset is the SWCLK alternate function with internal pull-down enabled, also USART2_TX.
38 PA15 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with alternate functions SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR and EVENTOUT.
39 PB3 bidirectional 5 V-tolerant I/O with alternate functions SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1 and EVENTOUT.
40 PB4 bidirectional 5 V-tolerant I/O with alternate functions SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2 and EVENTOUT.
41 PB5 bidirectional 5 V-tolerant I/O with alternate functions SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN and TIM3_CH2, and additional function WKUP6.
42 PB6 bidirectional 5 V-tolerant I/O, FM+ capable, with alternate functions I2C1_SCL, USART1_TX, TIM16_CH1N and TSC_G5_IO3.
43 PB7 bidirectional 5 V-tolerant I/O, FM+ capable, with alternate functions I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N and TSC_G5_IO4; I2C1 can sink 20 mA in Fast Mode Plus.
44 BOOT0 input Dedicated boot pin which, together with the boot selector option bit, selects user Flash, system memory or embedded SRAM as the boot source at startup.
45 PB8 bidirectional 5 V-tolerant I/O, FM+ capable, with alternate functions I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC and CAN_RX.
46 PB9 bidirectional 5 V-tolerant I/O, FM+ capable, with alternate functions SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT and CAN_TX.
47 VSS power_in Ground.
48 VDD power_in Digital power supply, 2.0 to 3.6 V, which also supplies the internal regulator.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-48(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: STM32F072CBU7
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f072cbu7-etched.step / stm32f072cbu7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f072cbu7.step / stm32f072cbu7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (128 pp, sha256 b01391f094699aeb, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF