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STM32F071RBT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f071rbt6factory-2.0.0extractor-text
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docs stm32f071rbt6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers stm32f071rbt6: viewers · Ray 9d ago
package.json Publish 0.1.0 · Ray 9d ago
page.json Set visibility: public · Ray 9d ago
README.md Initial commit: component/stm32f071rbt6 · Ray 9d ago
stm32f071rbt6-etched.fit.json stm32f071rbt6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
stm32f071rbt6-etched.glb stm32f071rbt6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
stm32f071rbt6-etched.step stm32f071rbt6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
stm32f071rbt6.glb Publish 0.1.0 · Ray 9d ago
stm32f071rbt6.kicad_mod Publish 0.1.0 · Ray 9d ago
stm32f071rbt6.kicad_sym Publish 0.1.0 · Ray 9d ago
stm32f071rbt6.lbr Publish 0.1.0 · Ray 9d ago
stm32f071rbt6.step Publish 0.1.0 · Ray 9d ago

STM32F071RBT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F071RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply for RTC and backup registers when VDD is not present, voltage range 1.65 to 3.6 V.
2 PC13 bidirectional Port C pin 13, configured as 3.3 V GPIO with RTC TAMP1, RTC_TS, RTC_OUT alternate functions.
3 PC14-OSC32_IN bidirectional Port C pin 14 / 32 kHz oscillator input, configured as 3.3 V GPIO with OSC32_IN alternate function.
4 PC15-OSC32_OUT bidirectional Port C pin 15 / 32 kHz oscillator output, configured as 3.3 V GPIO with OSC32_OUT alternate function.
5 PF0-OSC_IN bidirectional Port F pin 0 / HSE oscillator input, configured as 5 V tolerant GPIO with CRS_SYNC alternate function.
6 PF1-OSC_OUT bidirectional Port F pin 1 / HSE oscillator output, configured as 5 V tolerant GPIO.
7 NRST bidirectional Device reset pin with embedded weak pull-up resistor, bidirectional reset input/output active low.
8 PC0 bidirectional Port C pin 0, configured as 3.3 V GPIO connected to ADC input channel ADC_IN10.
9 PC1 bidirectional Port C pin 1, configured as 3.3 V GPIO connected to ADC input channel ADC_IN11.
10 PC2 bidirectional Port C pin 2, configured as 3.3 V GPIO connected to ADC input channel ADC_IN12 with SPI2_MISO alternate function.
11 PC3 bidirectional Port C pin 3, configured as 3.3 V GPIO connected to ADC input channel ADC_IN13 with SPI2_MOSI alternate function.
12 VSSA power_in Analog ground for ADC, DAC, and analog circuits.
13 VDDA power_in Analog power supply for ADC, DAC, and analog circuits, voltage range 2.4 to 3.6 V (minimum 2.4 V when ADC/DAC used).
14 PA0 bidirectional Port A pin 0, configured as 3.3 V GPIO connected to ADC channel ADC_IN0 with USART2_CTS, TIM2_CH1_ETR, TSC_G1_IO1 alternate functions.
15 PA1 bidirectional Port A pin 1, configured as 3.3 V GPIO connected to ADC channel ADC_IN1 with USART2_RTS, TIM2_CH2 alternate functions.
16 PA2 bidirectional Port A pin 2, configured as 3.3 V GPIO connected to ADC channel ADC_IN2 with USART2_TX, TIM2_CH3 alternate functions.
17 PA3 bidirectional Port A pin 3, configured as 3.3 V GPIO connected to ADC channel ADC_IN3 with USART2_RX, TIM2_CH4 alternate functions.
18 VSS power_in Digital ground, must be connected to external power supply ground.
19 VDD power_in Digital power supply for internal logic and I/O, voltage range 2.0 to 3.6 V.
20 PA4 bidirectional Port A pin 4, configured as 3.3 V GPIO connected to ADC channel ADC_IN4 with SPI1_NSS, TIM14_CH1, TSC_G2_IO1 alternate functions.
21 PA5 bidirectional Port A pin 5, configured as 3.3 V GPIO connected to ADC channel ADC_IN5 with SPI1_SCK, CEC, TIM2_CH1_ETR alternate functions.
22 PA6 bidirectional Port A pin 6, configured as 3.3 V GPIO connected to ADC channel ADC_IN6 with SPI1_MISO, TIM3_CH1, TIM1_BKIN alternate functions.
23 PA7 bidirectional Port A pin 7, configured as 3.3 V GPIO connected to ADC channel ADC_IN7 with SPI1_MOSI, TIM3_CH2, TIM14_CH1 alternate functions.
24 PC4 bidirectional Port C pin 4, configured as 3.3 V GPIO connected to ADC channel ADC_IN14 with USART3_TX alternate function.
25 PC5 bidirectional Port C pin 5, configured as 3.3 V GPIO connected to ADC channel ADC_IN15 with TSC_G3_IO1, USART3_RX alternate functions.
26 PB0 bidirectional Port B pin 0, configured as 3.3 V GPIO connected to ADC channel ADC_IN8 with TIM3_CH3, TIM1_CH2N alternate functions.
27 PB1 bidirectional Port B pin 1, configured as 3.3 V GPIO connected to ADC channel ADC_IN9 with TIM3_CH4, TIM14_CH1 alternate functions.
28 PB2 bidirectional Port B pin 2, configured as 5 V tolerant GPIO with TSC_G3_IO4 alternate function.
29 PB10 bidirectional Port B pin 10, configured as 5 V tolerant GPIO with SPI2_SCK, I2C2_SCL, USART3_TX, TSC_SYNC alternate functions.
30 PB11 bidirectional Port B pin 11, configured as 5 V tolerant GPIO with USART3_RX, TIM2_CH4, I2C2_SDA, TSC_G6_IO1 alternate functions.
31 VSS power_in Digital ground, must be connected to external power supply ground.
32 VDD power_in Digital power supply for internal logic and I/O, voltage range 2.0 to 3.6 V.
33 PB12 bidirectional Port B pin 12, configured as 5 V tolerant GPIO with TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK alternate functions.
34 PB13 bidirectional Port B pin 13, configured as 5 V tolerant FM+ capable GPIO with SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS alternate functions.
35 PB14 bidirectional Port B pin 14, configured as 5 V tolerant FM+ capable GPIO with SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS alternate functions.
36 PB15 bidirectional Port B pin 15, configured as 5 V tolerant GPIO with SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2 alternate functions.
37 PC6 bidirectional Port C pin 6, configured as 5 V tolerant GPIO supplied by VDDIO2 with TIM3_CH1 alternate function.
38 PC7 bidirectional Port C pin 7, configured as 5 V tolerant GPIO supplied by VDDIO2 with TIM3_CH2 alternate function.
39 PC8 bidirectional Port C pin 8, configured as 5 V tolerant GPIO supplied by VDDIO2 with TIM3_CH3 alternate function.
40 PC9 bidirectional Port C pin 9, configured as 5 V tolerant GPIO supplied by VDDIO2 with TIM3_CH4 alternate function.
41 PA8 bidirectional Port A pin 8, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART1_CK, TIM1_CH1, MCO, CRS_SYNC alternate functions.
42 PA9 bidirectional Port A pin 9, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART1_TX, TIM1_CH2, TIM15_BKIN, TSC_G4_IO1 alternate functions.
43 PA10 bidirectional Port A pin 10, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2 alternate functions.
44 PA11 bidirectional Port A pin 11, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3 alternate functions.
45 PA12 bidirectional Port A pin 12, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4 alternate functions.
46 PA13 bidirectional Port A pin 13, configured as 5 V tolerant GPIO supplied by VDDIO2 with SWDIO, IR_OUT alternate functions, internal pull-up active after reset.
47 VSS power_in Digital ground, must be connected to external power supply ground.
48 VDDIO2 power_in Independent I/O supply voltage for pins PC6-PC9, PA8-PA14, PD0-PD2, voltage range 1.65 to 3.6 V, must not be supplied without valid VDD.
49 PA14 bidirectional Port A pin 14, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART2_TX, SWCLK alternate functions, internal pull-down active after reset.
50 PA15 bidirectional Port A pin 15, configured as 5 V tolerant GPIO supplied by VDDIO2 with SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR alternate functions.
51 PC10 bidirectional Port C pin 10, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART3_TX, USART4_TX alternate function.
52 PC11 bidirectional Port C pin 11, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART3_RX, USART4_RX alternate function.
53 PC12 bidirectional Port C pin 12, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART3_CK, USART4_CK alternate function.
54 PD2 bidirectional Port D pin 2, configured as 5 V tolerant GPIO supplied by VDDIO2 with USART3_RTS, TIM3_ETR alternate functions.
55 PB3 bidirectional Port B pin 3, configured as 5 V tolerant GPIO with SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1 alternate functions.
56 PB4 bidirectional Port B pin 4, configured as 5 V tolerant GPIO with SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2 alternate functions.
57 PB5 bidirectional Port B pin 5, configured as 5 V tolerant GPIO with SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2 alternate functions.
58 PB6 bidirectional Port B pin 6, configured as 5 V tolerant FM+ capable GPIO with I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3 alternate functions.
59 PB7 bidirectional Port B pin 7, configured as 5 V tolerant FM+ capable GPIO with I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4 alternate functions.
60 BOOT0 input Boot mode selection pin, selects boot from user Flash, system memory, or embedded SRAM at startup, voltage range 0 to 9 V.
61 PB8 bidirectional Port B pin 8, configured as 5 V tolerant FM+ capable GPIO with I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC alternate functions.
62 PB9 bidirectional Port B pin 9, configured as 5 V tolerant FM+ capable GPIO with SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1 alternate functions.
63 VSS power_in Digital ground, must be connected to external power supply ground.
64 VDD power_in Digital power supply for internal logic and I/O, voltage range 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32F071RBT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f071rbt6-etched.step / stm32f071rbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f071rbt6.step / stm32f071rbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (122 pp, sha256 38af2b847d34deba, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF