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STM32F071CBU6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F071CBU6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32F071CBU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup power supply for RTC, 32 kHz oscillator and backup registers, 1.65 to 3.6 V when VDD is not present. |
| 2 | PC13 | bidirectional | TC I/O supplied through the power switch (3 mA sink limit), output speed max 2 MHz with 30 pF load and not usable as a current source; additional functions WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT. |
| 3 | PC14-OSC32_IN | bidirectional | TC I/O (PC14) supplied through the power switch with 2 MHz/30 pF output limit, also the OSC32_IN 32 kHz oscillator input. |
| 4 | PC15-OSC32_OUT | bidirectional | TC I/O (PC15) supplied through the power switch with 2 MHz/30 pF output limit, also the OSC32_OUT 32 kHz oscillator output. |
| 5 | PF0-OSC_IN | bidirectional | 5 V-tolerant I/O with alternate function CRS_SYNC, also the OSC_IN main oscillator input. |
| 6 | PF1-OSC_OUT | bidirectional | 5 V-tolerant I/O, also the OSC_OUT main oscillator output. |
| 7 | NRST | bidirectional | Device reset input / internal reset output (active low), bidirectional with embedded weak pull-up. |
| 8 | VSSA | power_in | Analog ground. |
| 9 | VDDA | power_in | Analog power supply from VDD to 3.6 V, minimum 2.4 V when ADC or DAC is used; must be established first and be at or above VDD. |
| 10 | PA0 | bidirectional | TTa I/O with USART2_CTS, TIM2_CH1_ETR, TSC_G1_IO1, USART4_TX; additional RTC_TAMP2, WKUP1, COMP1_OUT, ADC_IN0, COMP1_INM6. |
| 11 | PA1 | bidirectional | TTa I/O with USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, USART4_RX, EVENTOUT; additional ADC_IN1, COMP1_INP. |
| 12 | PA2 | bidirectional | TTa I/O with USART2_TX, TIM2_CH3, TIM15_CH1, TSC_G1_IO3; additional ADC_IN2, COMP2_OUT, COMP2_INM6, WKUP4. |
| 13 | PA3 | bidirectional | TTa I/O with USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4; additional ADC_IN3, COMP2_INP. |
| 14 | PA4 | bidirectional | TTa I/O with SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CK; additional COMP1_INM4, COMP2_INM4, ADC_IN4, DAC_OUT1. |
| 15 | PA5 | bidirectional | TTa I/O with SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2; additional COMP1_INM5, COMP2_INM5, ADC_IN5, DAC_OUT2. |
| 16 | PA6 | bidirectional | TTa I/O with SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT, USART3_CTS; additional ADC_IN6. |
| 17 | PA7 | bidirectional | TTa I/O with SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT, TSC_G2_IO4, EVENTOUT; additional ADC_IN7. |
| 18 | PB0 | bidirectional | TTa I/O with TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT, USART3_CK; additional ADC_IN8. |
| 19 | PB1 | bidirectional | TTa I/O with TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3; additional ADC_IN9. |
| 20 | PB2 | bidirectional | 5 V-tolerant I/O with TSC_G3_IO4. |
| 21 | PB10 | bidirectional | 5 V-tolerant I/O with SPI2_SCK, I2C2_SCL, USART3_TX, CEC, TSC_SYNC, TIM2_CH3. |
| 22 | PB11 | bidirectional | 5 V-tolerant I/O with USART3_RX, TIM2_CH4, EVENTOUT, TSC_G6_IO1, I2C2_SDA. |
| 23 | VSS | power_in | Ground. |
| 24 | VDD | power_in | Digital power supply, 2.0 to 3.6 V. |
| 25 | PB12 | bidirectional | 5 V-tolerant I/O with TIM1_BKIN, TIM15_BKIN, SPI2_NSS, I2S2_WS, USART3_CK, TSC_G6_IO2, EVENTOUT. |
| 26 | PB13 | bidirectional | 5 V-tolerant FM+ capable I/O with SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_CTS, TIM1_CH1N, TSC_G6_IO3. |
| 27 | PB14 | bidirectional | 5 V-tolerant FM+ capable I/O with SPI2_MISO, I2S2_MCK, I2C2_SDA, USART3_RTS, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4. |
| 28 | PB15 | bidirectional | 5 V-tolerant I/O with SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2; additional WKUP7, RTC_REFIN. |
| 29 | PA8 | bidirectional | 5 V-tolerant I/O supplied by VDDIO2 with USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC. |
| 30 | PA9 | bidirectional | 5 V-tolerant I/O supplied by VDDIO2 with USART1_TX, TIM1_CH2, TIM15_BKIN, TSC_G4_IO1. |
| 31 | PA10 | bidirectional | 5 V-tolerant I/O supplied by VDDIO2 with USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2. |
| 32 | PA11 | bidirectional | 5 V-tolerant I/O supplied by VDDIO2 with USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3, EVENTOUT. |
| 33 | PA12 | bidirectional | 5 V-tolerant I/O supplied by VDDIO2 with USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4, EVENTOUT. |
| 34 | PA13 | bidirectional | 5 V-tolerant I/O supplied by VDDIO2, SWDIO after reset with internal pull-up activated; also IR_OUT. |
| 35 | VSS | power_in | Ground. |
| 36 | VDDIO2 | power_in | Digital supply for the I/Os marked as VDDIO2, 1.65 to 3.6 V, independent of VDD but not to be provided without valid VDD. |
| 37 | PA14 | bidirectional | 5 V-tolerant I/O supplied by VDDIO2, SWCLK after reset with internal pull-down activated; also USART2_TX. |
| 38 | PA15 | bidirectional | 5 V-tolerant I/O supplied by VDDIO2 with SPI1_NSS, I2S1_WS, USART2_RX, USART4_RTS, TIM2_CH1_ETR, EVENTOUT. |
| 39 | PB3 | bidirectional | 5 V-tolerant I/O with SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT. |
| 40 | PB4 | bidirectional | 5 V-tolerant I/O with SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT. |
| 41 | PB5 | bidirectional | 5 V-tolerant I/O with SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2; additional WKUP6. |
| 42 | PB6 | bidirectional | 5 V-tolerant FM+ capable I/O with I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3. |
| 43 | PB7 | bidirectional | 5 V-tolerant FM+ capable I/O with I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N, TSC_G5_IO4. |
| 44 | BOOT0 | input | Dedicated boot memory selection input. |
| 45 | PB8 | bidirectional | 5 V-tolerant FM+ capable I/O with I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC. |
| 46 | PB9 | bidirectional | 5 V-tolerant FM+ capable I/O with SPI2_NSS, I2S2_WS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT. |
| 47 | VSS | power_in | Ground. |
| 48 | VDD | power_in | Digital power supply, 2.0 to 3.6 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
STM32F071CBU6 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32f071cbu6-etched.step/stm32f071cbu6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f071cbu6.step/stm32f071cbu6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (122 pp, sha256
054f3806403d4305, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).