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STM32F042K6T7

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F042K6T7

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM32F042K6T7 from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Digital power supply, VDD = VDDIO1 = 2.0 to 3.6 V, for I/Os and the internal regulator.
2 PF0-OSC_IN bidirectional 5 V-tolerant FM+ capable I/O (FTf) that is the HSE oscillator input after reset; alternate functions CRS_SYNC and I2C1_SDA.
3 PF1-OSC_OUT bidirectional 5 V-tolerant FM+ capable I/O (FTf) that is the HSE oscillator output after reset; alternate function I2C1_SCL.
4 NRST bidirectional Device reset input / internal reset output (active low), bidirectional with embedded weak pull-up resistor.
5 VDDA power_in Analog power supply, from VDD to 3.6 V (minimum 2.4 V when the ADC is used), must be established first and be at least VDD.
6 PA0 bidirectional TTa I/O with USART2_CTS, TIM2_CH1_ETR, TSC_G1_IO1; additional functions RTC_TAMP2, WKUP1, ADC_IN0.
7 PA1 bidirectional TTa I/O with USART2_RTS, TIM2_CH2, TSC_G1_IO2, EVENTOUT; additional function ADC_IN1.
8 PA2 bidirectional TTa I/O with USART2_TX, TIM2_CH3, TSC_G1_IO3; additional functions ADC_IN2, WKUP4.
9 PA3 bidirectional TTa I/O with USART2_RX, TIM2_CH4, TSC_G1_IO4; additional function ADC_IN3.
10 PA4 bidirectional TTa I/O with SPI1_NSS, I2S1_WS, TIM14_CH1, TSC_G2_IO1, USART2_CK, USB_NOE; additional function ADC_IN4.
11 PA5 bidirectional TTa I/O with SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR, TSC_G2_IO2; additional function ADC_IN5.
12 PA6 bidirectional TTa I/O with SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, TSC_G2_IO3, EVENTOUT; additional function ADC_IN6.
13 PA7 bidirectional TTa I/O with SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, TSC_G2_IO4, EVENTOUT; additional function ADC_IN7.
14 PB0 bidirectional TTa I/O with TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT; additional function ADC_IN8.
15 PB1 bidirectional TTa I/O with TIM3_CH4, TIM14_CH1, TIM1_CH3N, TSC_G3_IO3; additional function ADC_IN9.
16 VSS power_in Ground.
17 VDDIO2 power_in Independent digital supply of 1.65 to 3.6 V for PA8-PA15; must not be provided without a valid supply on VDD.
18 PA8 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with USART1_CK, TIM1_CH1, EVENTOUT, MCO, CRS_SYNC.
19 PA9 bidirectional 5 V-tolerant FM+ I/O supplied by VDDIO2 with USART1_TX, TIM1_CH2, TSC_G4_IO1, I2C1_SCL.
20 PA10 bidirectional 5 V-tolerant FM+ I/O supplied by VDDIO2 with USART1_RX, TIM1_CH3, TIM17_BKIN, TSC_G4_IO2, I2C1_SDA.
21 PA11 bidirectional 5 V-tolerant FM+ I/O supplied by VDDIO2 with CAN_RX, USART1_CTS, TIM1_CH4, TSC_G4_IO3, EVENTOUT, I2C1_SCL; additional function USB_DM.
22 PA12 bidirectional 5 V-tolerant FM+ I/O supplied by VDDIO2 with CAN_TX, USART1_RTS, TIM1_ETR, TSC_G4_IO4, EVENTOUT, I2C1_SDA; additional function USB_DP.
23 PA13 bidirectional 5 V-tolerant I/O supplied by VDDIO2, SWDIO after reset with internal pull-up activated; also IR_OUT, USB_NOE.
24 PA14 bidirectional 5 V-tolerant I/O supplied by VDDIO2, SWCLK after reset with internal pull-down activated; also USART2_TX.
25 PA15 bidirectional 5 V-tolerant I/O supplied by VDDIO2 with SPI1_NSS, I2S1_WS, USART2_RX, TIM2_CH1_ETR, EVENTOUT, USB_NOE.
26 PB3 bidirectional 5 V-tolerant I/O with SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1, EVENTOUT.
27 PB4 bidirectional 5 V-tolerant I/O with SPI1_MISO, I2S1_MCK, TIM17_BKIN, TIM3_CH1, TSC_G5_IO2, EVENTOUT.
28 PB5 bidirectional 5 V-tolerant I/O with SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN, TIM3_CH2; additional function WKUP6.
29 PB6 bidirectional 5 V-tolerant FM+ I/O with I2C1_SCL, USART1_TX, TIM16_CH1N, TSC_G5_IO3.
30 PB7 bidirectional 5 V-tolerant FM+ I/O with I2C1_SDA, USART1_RX, TIM17_CH1N, TSC_G5_IO4.
31 PB8-BOOT0 bidirectional 5 V-tolerant FM+ I/O used for boot memory selection (BOOT0), with I2C1_SCL, CEC, TIM16_CH1, TSC_SYNC, CAN_RX.
32 VSS/VSSA power_in Ground; the VSSA pad of the die is connected to this VSS pin as there is no distinct VSSA pin on this package.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

CAD (KiCad official)

  • Symbol: STM32F042K6T7
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f042k6t7-etched.step / stm32f042k6t7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f042k6t7.step / stm32f042k6t7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (117 pp, sha256 7af7ec8f5a596b23, retrieved 2026-10-03, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF