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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM32F042C6T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32F042C6T6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Backup power supply for RTC and backup registers, operating range 1.65 to 3.6 V.
2	PC13	bidirectional	3.3 V tolerant GPIO port C pin 13 supporting RTC tamper detection 1, timestamp trigger, RTC output, and wakeup trigger 2.
3	PC14	bidirectional	3.3 V tolerant GPIO port C pin 14 with alternate function 32.768 kHz oscillator input.
4	PC15	bidirectional	3.3 V tolerant GPIO port C pin 15 with alternate function 32.768 kHz oscillator output.
5	PF0	bidirectional	5 V-tolerant FM+ capable I/O supporting 8-32 MHz oscillator input and I2C1 serial data alternate functions.
6	PF1	bidirectional	5 V-tolerant FM+ capable I/O supporting 8-32 MHz oscillator output and I2C1 serial clock alternate functions.
7	NRST	bidirectional	Active-low device reset input with embedded pull-up resistor and RC filter for debouncing.
8	VSSA	power_in	Analog ground reference pin for ADC converter and internal analog circuits.
9	VDDA	power_in	Analog power supply pin, operating range 2.4 to 3.6 V when ADC is used, must be >= VDD.
10	PA0	bidirectional	3.3 V ADC-capable GPIO port A pin 0 supporting USART2_CTS, TIM2 channel 1, TSC group 1, RTC tamper 2, and wakeup 1.
11	PA1	bidirectional	3.3 V ADC-capable GPIO port A pin 1 supporting USART2_RTS, TIM2 channel 2, and TSC group 1 I/O2.
12	PA2	bidirectional	3.3 V ADC-capable GPIO port A pin 2 supporting USART2_TX, TIM2 channel 3, TSC group 1 I/O3, and wakeup trigger 4.
13	PA3	bidirectional	3.3 V ADC-capable GPIO port A pin 3 supporting USART2_RX, TIM2 channel 4, and TSC group 1 I/O4.
14	PA4	bidirectional	3.3 V ADC-capable GPIO port A pin 4 supporting SPI1 NSS, I2S1 word select, TIM14, TSC group 2, and USART2_CK.
15	PA5	bidirectional	3.3 V ADC-capable GPIO port A pin 5 supporting SPI1 SCK, I2S1 clock, CEC data, TIM2 channel 1, and TSC group 2 I/O2.
16	PA6	bidirectional	3.3 V ADC-capable GPIO port A pin 6 supporting SPI1 MISO, I2S1 master clock, TIM3 channel 1, TIM1 brake, TIM16 channel 1, and TSC group 2.
17	PA7	bidirectional	3.3 V ADC-capable GPIO port A pin 7 supporting SPI1 MOSI, I2S1 serial data, TIM3 channel 2, TIM1 channel 1N, TIM14, TIM17, and TSC group 2 I/O4.
18	PB0	bidirectional	3.3 V ADC-capable GPIO port B pin 0 supporting TIM3 channel 3, TIM1 channel 2N, and TSC group 3 I/O2.
19	PB1	bidirectional	3.3 V ADC-capable GPIO port B pin 1 supporting TIM3 channel 4, TIM1 channel 3N, TIM14, and TSC group 3 I/O3.
20	PB2	bidirectional	5 V-tolerant GPIO port B pin 2 supporting TSC group 3 I/O4.
21	PB10	bidirectional	5 V-tolerant FM+ capable I/O port B pin 10 supporting SPI2 SCK, CEC data, TSC sync, TIM2 channel 3, and I2C1 clock.
22	PB11	bidirectional	5 V-tolerant FM+ capable I/O port B pin 11 supporting TIM2 channel 4 and I2C1 serial data.
23	VSS	power_in	Ground reference pin for digital circuits and core logic.
24	VDD	power_in	Digital power supply pin for core logic and I/O, operating range 2.0 to 3.6 V.
25	PB12	bidirectional	5 V-tolerant GPIO port B pin 12 supporting TIM1 brake input and SPI2 NSS.
26	PB13	bidirectional	5 V-tolerant FM+ capable I/O port B pin 13 supporting SPI2 SCK, TIM1 channel 1N, and I2C1 clock.
27	PB14	bidirectional	5 V-tolerant FM+ capable I/O port B pin 14 supporting SPI2 MISO, TIM1 channel 2N, and I2C1 serial data.
28	PB15	bidirectional	5 V-tolerant GPIO port B pin 15 supporting SPI2 MOSI, TIM1 channel 3N, RTC reference input, and wakeup trigger 7.
29	PA8	bidirectional	5 V-tolerant GPIO port A pin 8 supplied by VDDIO2, supporting USART1 clock, TIM1 channel 1, MCO output, and CRS sync.
30	PA9	bidirectional	5 V-tolerant FM+ capable I/O port A pin 9 supplied by VDDIO2, supporting USART1 TX, TIM1 channel 2, TSC group 4, and I2C1 clock.
31	PA10	bidirectional	5 V-tolerant FM+ capable I/O port A pin 10 supplied by VDDIO2, supporting USART1 RX, TIM1 channel 3, TIM17 brake, TSC group 4, and I2C1 data.
32	PA11	bidirectional	5 V-tolerant FM+ capable I/O port A pin 11 supplied by VDDIO2, supporting CAN RX, USART1 CTS, TIM1 channel 4, I2C1 clock, and USB DM.
33	PA12	bidirectional	5 V-tolerant FM+ capable I/O port A pin 12 supplied by VDDIO2, supporting CAN TX, USART1 RTS, TIM1 external trigger, I2C1 data, and USB DP.
34	PA13	bidirectional	5 V-tolerant GPIO port A pin 13 supplied by VDDIO2, SWDIO serial wire debug interface after reset, supports IR output.
35	VSS	power_in	Ground reference pin for digital circuits and core logic.
36	VDDIO2	power_in	Digital I/O power supply for pins PA8-PA15, operating range 1.65 to 3.6 V, monitored with VREFINT threshold.
37	PA14	bidirectional	5 V-tolerant GPIO port A pin 14 supplied by VDDIO2, SWCLK serial wire debug clock after reset, supports USART2 TX.
38	PA15	bidirectional	5 V-tolerant GPIO port A pin 15 supplied by VDDIO2, supporting SPI1 NSS, I2S1 word select, USART2 RX, TIM2 channel 1, and USB disable.
39	PB3	bidirectional	5 V-tolerant GPIO port B pin 3 supporting SPI1 SCK, I2S1 clock, TIM2 channel 2, and TSC group 5 I/O1.
40	PB4	bidirectional	5 V-tolerant GPIO port B pin 4 supporting SPI1 MISO, I2S1 master clock, TIM17 brake, TIM3 channel 1, and TSC group 5 I/O2.
41	PB5	bidirectional	5 V-tolerant GPIO port B pin 5 supporting SPI1 MOSI, I2S1 serial data, I2C1 SMBA, TIM16 brake, TIM3 channel 2, and wakeup trigger 6.
42	PB6	bidirectional	5 V-tolerant FM+ capable I/O port B pin 6 supporting I2C1 clock, USART1 TX, TIM16 channel 1N, and TSC group 5 I/O3.
43	PB7	bidirectional	5 V-tolerant FM+ capable I/O port B pin 7 supporting I2C1 serial data, USART1 RX, TIM17 channel 1N, and TSC group 5 I/O4.
44	PF11	bidirectional	5 V-tolerant GPIO port F pin 11 used for Boot0 memory selection between flash and system bootloader.
45	PB8	bidirectional	5 V-tolerant FM+ capable I/O port B pin 8 supporting I2C1 clock, CEC data, TIM16 channel 1, TSC sync, and CAN RX.
46	PB9	bidirectional	5 V-tolerant FM+ capable I/O port B pin 9 supporting SPI2 NSS, I2C1 data, IR output, TIM17 channel 1, and CAN TX.
47	VSS	power_in	Ground reference pin for digital circuits and core logic.
48	VDD	power_in	Digital power supply pin for core logic and I/O, operating range 2.0 to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

CAD (KiCad official)

Symbol: STM32F042C6T6
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: stm32f042c6t6-etched.step / stm32f042c6t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f042c6t6.step / stm32f042c6t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (117 pp, sha256 7af7ec8f5a596b23, retrieved 2026-09-24, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF