STM32C071RBT6

STMICROELECTRONICS · Global Sourcing Parts · LQFP-64(10x10)

STM32C071RBT6 from STMICROELECTRONICS, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PC11	bidirectional	5 V-tolerant (FT) I/O with alternate function TIM1_CH4.
2	PC12	bidirectional	5 V-tolerant (FT) I/O with alternate function TIM14_CH1.
3	PC13	bidirectional	5 V-tolerant (FT) I/O with alternate functions TIM1_ETR and TIM1_BKIN, and additional functions RTC_TS, RTC_OUT1 and WKUP2.
4	PC14-OSCX_IN	bidirectional	5 V-tolerant (FT_f, Fm+ capable) I/O with additional function OSCX_IN, and alternate functions including USART1_TX, TIM1_ETR, TIM1_BKIN2, IR_OUT, TIM17_CH1, TIM3_CH2, SPI2_NSS, I2C1_SDA and EVENTOUT.
5	PC15-OSCX_OUT	bidirectional	5 V-tolerant (FT) I/O with additional function OSCX_OUT, and alternate functions OSC32_EN, OSC_EN, TIM1_ETR and TIM3_CH3.
6	PF3	bidirectional	5 V-tolerant (FT) I/O with no alternate function listed in the pin table.
7	VREF+	power_in	Dedicated positive reference voltage for the ADC, from 2 V up to VDD; on packages without this pin VREF+ is internally connected to VDDA.
8	VDD/VDDA	power_in	Main supply (VDD) and analog supply (VDDA) of 2.0 V to 3.6 V, to be decoupled with filtering ceramic capacitors placed close to the pins.
9	VSS/VSSA	power_in	Ground pin for the digital (VSS) and analog (VSSA) supplies.
10	PF0-OSC_IN	bidirectional	5 V-tolerant (FT) I/O with additional function OSC_IN, and alternate functions CRS_SYNC and TIM14_CH1.
11	PF1-OSC_OUT	bidirectional	5 V-tolerant (FT) I/O with additional function OSC_OUT and alternate function OSC_EN.
12	PF2-NRST	bidirectional	Reset pin with embedded weak pull-up (RST I/O structure) when configured as reset, and 5 V-tolerant FT GPIO when configured as GPIO; alternate functions MCO and TIM1_CH4, additional function NRST.
13	PC0	bidirectional	5 V-tolerant (FT) I/O with no alternate function listed in the pin table.
14	PC1	bidirectional	5 V-tolerant (FT) I/O with no alternate function listed in the pin table.
15	PC2	bidirectional	5 V-tolerant (FT) I/O with alternate function SPI2_MISO.
16	PC3	bidirectional	5 V-tolerant (FT) I/O with alternate function SPI2_MOSI.
17	PA0	bidirectional	5 V-tolerant (FT_a) I/O with analog switch function, additional functions ADC_IN0 and WKUP1, and alternate functions including SPI2_SCK, USART2_CTS/USART2_NSS, TIM16_CH1, TIM2_ETR/TIM2_CH1, USART1_TX and TIM1_CH1.
18	PA1	bidirectional	5 V-tolerant (FT_a) I/O with additional function ADC_IN1, and alternate functions including SPI1_SCK/I2S1_CK, USART2_RTS/USART2_DE/USART2_CK, TIM17_CH1, TIM2_CH2, USART1_RX, TIM1_CH2, I2C1_SMBA and EVENTOUT.
19	PA2	bidirectional	5 V-tolerant (FT_a) I/O with additional functions ADC_IN2, WKUP4 and LSCO, and alternate functions including SPI1_MOSI/I2S1_SD, USART2_TX, TIM16_CH1N, TIM3_ETR, TIM1_CH3 and TIM2_CH3.
20	PA3	bidirectional	5 V-tolerant (FT_a) I/O with additional function ADC_IN3, and alternate functions including SPI2_MISO, USART2_RX, TIM1_CH1N, TIM2_CH4, TIM1_CH4 and EVENTOUT.
21	PA4	bidirectional	5 V-tolerant (FT_a) I/O with additional functions ADC_IN4 and RTC_OUT2, and alternate functions including SPI1_NSS/I2S1_WS, USART2_TX, TIM1_CH2N, SPI2_MOSI, TIM14_CH1, TIM17_CH1N, USB_NOE and EVENTOUT.
22	PA5	bidirectional	5 V-tolerant (FT_a) I/O with additional function ADC_IN5, and alternate functions including SPI1_SCK/I2S1_CK, USART2_RX, TIM1_CH3N, TIM2_ETR/TIM2_CH1, TIM1_CH1 and EVENTOUT.
23	PA6	bidirectional	5 V-tolerant (FT_fa) I/O, Fm+ capable with analog switch, additional function ADC_IN6, and alternate functions including SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1 and I2C2_SDA.
24	PA7	bidirectional	5 V-tolerant (FT_fa) I/O, Fm+ capable with analog switch, additional function ADC_IN7, and alternate functions including SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1 and I2C2_SCL.
25	PC4	bidirectional	5 V-tolerant (FT_a) I/O with additional function ADC_IN11, and alternate functions USART1_TX and TIM2_ETR/TIM2_CH1.
26	PC5	bidirectional	5 V-tolerant (FT_a) I/O with additional functions ADC_IN12 and WKUP5, and alternate functions USART1_RX and TIM2_CH2.
27	PB0	bidirectional	5 V-tolerant (FT_a) I/O with additional function ADC_IN17, and alternate functions SPI1_NSS/I2S1_WS, TIM3_CH3 and TIM1_CH2N.
28	PB1	bidirectional	5 V-tolerant (FT_a) I/O with additional function ADC_IN18, and alternate functions TIM14_CH1, TIM3_CH4, TIM1_CH3N, TIM1_CH2N and EVENTOUT.
29	PB2	bidirectional	5 V-tolerant (FT_a) I/O with additional function ADC_IN19, and alternate functions USART1_RX, MCO2, SPI2_MISO and EVENTOUT.
30	PB10	bidirectional	5 V-tolerant (FT_fa) I/O, Fm+ capable with analog switch, additional function ADC_IN20, and alternate functions TIM2_CH3, SPI2_SCK and I2C2_SCL.
31	PB11	bidirectional	5 V-tolerant (FT_fa) I/O, Fm+ capable with analog switch, additional function ADC_IN21, and alternate functions SPI2_MOSI, TIM2_CH4 and I2C2_SDA.
32	PB12	bidirectional	5 V-tolerant (FT_a) I/O with additional function ADC_IN22, and alternate functions SPI2_NSS, TIM1_BKIN2, TIM1_BKIN and EVENTOUT.
33	PB13	bidirectional	5 V-tolerant (FT_sfa) I/O, Fm+ capable with analog switch, supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI2_SCK, TIM1_CH1N, I2C2_SCL and EVENTOUT.
34	PB14	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI2_MISO, TIM1_CH2N, I2C2_SDA and EVENTOUT.
35	PB15	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI2_MOSI, TIM1_CH3N and EVENTOUT, and additional function RTC_REFIN.
36	PA8	bidirectional	5 V-tolerant (FT_sa) I/O with analog switch, supplied only by VDDIO2 (internally connected to VDD on the GP package), additional function ADC_IN8, and alternate functions including MCO, USART2_TX, TIM1_CH1, SPI2_NSS, CRS_SYNC, TIM14_CH1 and USART1_RX.
37	PA9	bidirectional	5 V-tolerant (FT_sf) Fm+ capable I/O supplied by VDDIO2 (internally connected to VDD on the GP package), with alternate functions MCO, USART1_TX, TIM1_CH2, TIM3_ETR, SPI2_MISO, I2C1_SCL, EVENTOUT and I2C2_SCL; it can be remapped in place of PA11 via SYSCFG_CFGR1.
38	PC6	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_CH1 and TIM2_CH3.
39	PC7	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_CH2 and TIM2_CH4.
40	PD8	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate function SPI1_SCK/I2S1_CK.
41	PD9	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI1_NSS/I2S1_WS and TIM1_BKIN2.
42	PA10	bidirectional	5 V-tolerant (FT_sf) Fm+ capable I/O supplied by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI2_MOSI, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT and I2C2_SDA.
43	PA11 [PA9]	bidirectional	5 V-tolerant (FT_usf) Fm+ capable I/O with USB function USB_DM, and alternate functions SPI1_MISO/I2S1_MCK, USART1_CTS/USART1_NSS, TIM1_CH4, TIM1_BKIN2 and I2C2_SCL; PA9 can be remapped in its place via SYSCFG_CFGR1.
44	PA12 [PA10]	bidirectional	5 V-tolerant (FT_usf) Fm+ capable I/O with USB function USB_DP, and alternate functions SPI1_MOSI/I2S1_SD, USART1_RTS/USART1_DE/USART1_CK, TIM1_ETR, I2S_CKIN and I2C2_SDA; PA10 can be remapped in its place via SYSCFG_CFGR1.
45	PA13	bidirectional	5 V-tolerant (FT_sa) I/O with analog switch, configured as SWDIO after reset with internal pull-up enabled; additional function ADC_IN13, and alternate functions IR_OUT, USB_NOE, TIM3_ETR, USART2_RX and EVENTOUT.
46	PA14-BOOT0	bidirectional	5 V-tolerant (FT_sa) I/O with analog switch, configured as SWCLK after reset with internal pull-down enabled; additional functions ADC_IN14 and BOOT0, and alternate functions USART2_TX, EVENTOUT, SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, MCO2 and USART1_RTS/USART1_DE/USART1_CK.
47	PA15	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, MCO2, USART1_RTS/USART1_DE/USART1_CK, TIM2_ETR/TIM2_CH1, USB_NOE and EVENTOUT.
48	PC8	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_CH3 and TIM1_CH1.
49	PC9	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_CH4, TIM1_CH2, I2S_CKIN and USB_NOE.
50	PD0	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions EVENTOUT, TIM16_CH1 and SPI2_NSS.
51	PD1	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions EVENTOUT, TIM17_CH1 and SPI2_SCK.
52	PD2	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_ETR and TIM1_CH1N.
53	PD3	bidirectional	5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions USART2_CTS/USART2_NSS, TIM1_CH2N and SPI2_MISO.
54	PD4	bidirectional	5 V-tolerant (FT) I/O with alternate functions SPI2_MOSI, USART2_RTS/USART2_DE/USART2_CK and TIM1_CH3N.
55	PD5	bidirectional	5 V-tolerant (FT) I/O with alternate functions SPI1_MISO/I2S1_MCK, USART2_TX and TIM1_BKIN.
56	PD6	bidirectional	5 V-tolerant (FT) I/O with alternate functions SPI1_MOSI/I2S1_SD and USART2_RX.
57	PB3	bidirectional	5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions SPI1_SCK/I2S1_CK, TIM1_CH2, TIM3_CH2, USART1_RTS/USART1_DE/USART1_CK, I2C2_SCL, TIM2_CH2 and EVENTOUT.
58	PB4	bidirectional	5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS/USART1_NSS, TIM17_BKIN, I2C2_SDA and EVENTOUT.
59	PB5	bidirectional	5 V-tolerant (FT) I/O with additional function WKUP6, and alternate functions SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, TIM3_CH3 and I2C1_SMBA.
60	PB6	bidirectional	5 V-tolerant (FT_f) Fm+ capable I/O with additional function WKUP3, and alternate functions USART1_TX, TIM1_CH3, TIM16_CH1N, TIM3_CH3, SPI2_MISO, USART1_NSS/USART1_CTS, I2C1_SCL and I2C1_SMBA, among others.
61	PB7	bidirectional	5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions USART1_RX, TIM1_CH4, TIM17_CH1N, TIM3_CH4, SPI2_MOSI, I2C1_SDA, EVENTOUT, USART2_CTS/USART2_NSS, TIM16_CH1, TIM3_CH1 and I2C1_SCL.
62	PB8	bidirectional	5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions USART2_CTS/USART2_NSS, TIM16_CH1, TIM3_CH1, SPI2_SCK, I2C1_SCL and EVENTOUT.
63	PB9	bidirectional	5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions IR_OUT, USART2_RTS/USART2_DE/USART2_CK, TIM17_CH1, TIM3_CH2, SPI2_NSS, I2C1_SDA and EVENTOUT.
64	PC10	bidirectional	5 V-tolerant (FT) I/O with alternate function TIM1_CH3.

Key specifications

Parameter	Value
Manufacturer	STMICROELECTRONICS
Package	LQFP-64(10x10)
Category	Global Sourcing Parts
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
External supply voltage	VDD	-0.3		4	V		51
External supply voltage for selected I/Os	VDDIO2	-0.3		4	V		51
External voltage on VREF+ pin	VREF+	-0.3			V		51
Input voltage on pin	VIN	-0.3			V		51
Current into VDD/VDDA and VDDIO2 power pins (source)	IVDD/VDDA,VDDIO2			100	mA		51
Current out of VSS/VSSA ground pin (sink)	IVSS/VSSA			100	mA		51
Output current sunk by any I/O and control pin	IIO(PIN)			20	mA	Output current sunk by any I/O and control pin	51
Output current sourced by any I/O and control pin	IIO(PIN)			20	mA	Output current sourced by any I/O and control pin	51
Total output current sunk by sum of all I/Os and control pins	∑I(PIN)			80	mA	Total output current sunk by sum of all I/Os and control pins	51
Total output current sourced by sum of all I/Os and control pins	∑I(PIN)			80	mA	Total output current sourced by sum of all I/Os and control pins	51
Injected current on a FT_xx pin (negative injection; positive not applicable)	IINJ(PIN)			-5	mA	Injected current on a FT_xx pin; positive NA	52
Total injected current (sum of all I/Os and control pins)	∑IINJ(PIN)			-25	mA		52
Storage temperature range	TSTG	-65		150	°C		52
Maximum junction temperature	TJ			130	°C		52
Standard operating voltage	VDD	2		3.6	V		53
External supply voltage for selected I/Os	VDDIO2	1.65		3.6	V		53
I/O input voltage	VIN	-0.3			V		53
AHB clock frequency	fHCLK			48	MHz		53
APB clock frequency	fPCLK			48	MHz		53
Ambient temperature (suffix 6)	TA	-40		85	°C	Suffix 6	53
Junction temperature (suffix 6)	TJ	-40		105	°C	Suffix 6	53
VDD rise time rate	tVDD	0			µs/V		53
VDD fall time rate	tVDD	10			µs/V		53
POR temporization when VDD crosses VPOR	tRSTTEMPO		270	500	µs	VDD rising	54
Power-on reset threshold	VPOR	1.9	1.94	1.98	V		54
Power-down reset threshold	VPDR	1.88	1.92	1.96	V		54
Brownout reset threshold 1	VBOR1	2.05	2.1	2.18	V	VDD rising	54
Brownout reset threshold 1	VBOR1	1.95	2	2.08	V	VDD falling	54
Brownout reset threshold 2	VBOR2	2.2	2.31	2.38	V	VDD rising	54
Brownout reset threshold 2	VBOR2	2.1	2.21	2.28	V	VDD falling	54
Brownout reset threshold 3	VBOR3	2.5	2.62	2.68	V	VDD rising	54
Brownout reset threshold 3	VBOR3	2.4	2.52	2.58	V	VDD falling	54
Brownout reset threshold 4	VBOR4	2.8	2.91	3	V	VDD rising	54
Brownout reset threshold 4	VBOR4	2.7	2.81	2.9	V	VDD falling	54
Internal reference voltage	VREFINT	1.182	1.212	1.232	V		54
Internal reference voltage spread over the temperature range	∆VREFINT		30	50	mV	VDD = 3 V	54
Average temperature coefficient	TCoeff		20	70	ppm/°C		54
Long term stability	ACoeff		300	1000	ppm	1000 hours, T = 25 °C	54
Voltage coefficient	VDDCoeff		250	1200	ppm/V	3.0 V < VDD < 3.6 V	54
Weak pull-up equivalent resistor	RPU	25	40	55	kΩ	VIN = VSS	79
Weak pull-down equivalent resistor	RPD	25	40	55	kΩ	VIN = VDDIOx	79
Output low level voltage, CMOS port	VOL			0.4	V	/IIO/ = 8 mA, VDDIOx ≥ 2.7 V	81
Output high level voltage, TTL port	VOH	2.4			V		81
NRST weak pull-up equivalent resistor	RPU	25	40	55	kΩ	VIN = VSS	83
NRST input filtered pulse	VF(NRST)			70	ns	2.0 V < VDD < 3.6 V	83
NRST input not filtered pulse	VNF(NRST)	350			ns	2.0 V < VDD < 3.6 V	83
Analog supply voltage	VDDA	2		3.6	V		84
ADC clock frequency	fADC	0.14		35	MHz		84
Sampling rate, 12 bits	fs			2.5	MSps	12 bits	84
HSI48 frequency	fHSI48	47.92		48.4	MHz	VDD=3.0 V, TA=30 °C	72
HSI48 oscillator frequency drift over temperature and VDD full voltage range	∆Temp(HSI)	-1		1	%	TA= 0 to 85 °C	72
HSI48 oscillator frequency drift over temperature and VDD full voltage range	∆Temp(HSI)	-2.5		2	%	TA= -40 to 125 °C	72
HSIUSB48 frequency	fHSIUSB48		48		MHz	VDD = 3.0 V, TA = 30 °C	73
HSIUSB48 oscillator accuracy over temperature (factory calibrated)	ACCHSIUSB48_REL	-3		3	%	VDD = 3.0 V to 3.6 V, TA = -15 to 85 °C	73
HSIUSB48 oscillator accuracy over temperature (factory calibrated)	ACCHSIUSB48_REL	-4.5		4.5	%	VDD = 2.0 V to 3.6 V, TA = -40 to 125 °C	73
LSI frequency	fLSI	31.04	32	32.96	kHz	VDD = 3.3 V, TA = 25 °C	74
LSI frequency	fLSI	29.5		34	kHz	VDD = 2 V to 3.6 V, TA = -40 to 125 °C	74
Endurance	NEND	10			kcycles	TJ = -40 to +130 °C	75
I/O pin capacitance	CIO		5		pF		79
NRST input Schmitt trigger voltage hysteresis	Vhys(NRST)		200		mV		83

CAD (KiCad official)

Symbol: STM32C071RBT6
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: stm32c071rbt6-etched.step / stm32c071rbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32c071rbt6.step / stm32c071rbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMICROELECTRONICS datasheet (129 pp, sha256 47df10c3b7af4b1b, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# STM32C071RBT6

**STMICROELECTRONICS** · Global Sourcing Parts · LQFP-64(10x10)

STM32C071RBT6 from STMICROELECTRONICS, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC11 | bidirectional | 5 V-tolerant (FT) I/O with alternate function TIM1_CH4. |
| 2 | PC12 | bidirectional | 5 V-tolerant (FT) I/O with alternate function TIM14_CH1. |
| 3 | PC13 | bidirectional | 5 V-tolerant (FT) I/O with alternate functions TIM1_ETR and TIM1_BKIN, and additional functions RTC_TS, RTC_OUT1 and WKUP2. |
| 4 | PC14-OSCX_IN | bidirectional | 5 V-tolerant (FT_f, Fm+ capable) I/O with additional function OSCX_IN, and alternate functions including USART1_TX, TIM1_ETR, TIM1_BKIN2, IR_OUT, TIM17_CH1, TIM3_CH2, SPI2_NSS, I2C1_SDA and EVENTOUT. |
| 5 | PC15-OSCX_OUT | bidirectional | 5 V-tolerant (FT) I/O with additional function OSCX_OUT, and alternate functions OSC32_EN, OSC_EN, TIM1_ETR and TIM3_CH3. |
| 6 | PF3 | bidirectional | 5 V-tolerant (FT) I/O with no alternate function listed in the pin table. |
| 7 | VREF+ | power_in | Dedicated positive reference voltage for the ADC, from 2 V up to VDD; on packages without this pin VREF+ is internally connected to VDDA. |
| 8 | VDD/VDDA | power_in | Main supply (VDD) and analog supply (VDDA) of 2.0 V to 3.6 V, to be decoupled with filtering ceramic capacitors placed close to the pins. |
| 9 | VSS/VSSA | power_in | Ground pin for the digital (VSS) and analog (VSSA) supplies. |
| 10 | PF0-OSC_IN | bidirectional | 5 V-tolerant (FT) I/O with additional function OSC_IN, and alternate functions CRS_SYNC and TIM14_CH1. |
| 11 | PF1-OSC_OUT | bidirectional | 5 V-tolerant (FT) I/O with additional function OSC_OUT and alternate function OSC_EN. |
| 12 | PF2-NRST | bidirectional | Reset pin with embedded weak pull-up (RST I/O structure) when configured as reset, and 5 V-tolerant FT GPIO when configured as GPIO; alternate functions MCO and TIM1_CH4, additional function NRST. |
| 13 | PC0 | bidirectional | 5 V-tolerant (FT) I/O with no alternate function listed in the pin table. |
| 14 | PC1 | bidirectional | 5 V-tolerant (FT) I/O with no alternate function listed in the pin table. |
| 15 | PC2 | bidirectional | 5 V-tolerant (FT) I/O with alternate function SPI2_MISO. |
| 16 | PC3 | bidirectional | 5 V-tolerant (FT) I/O with alternate function SPI2_MOSI. |
| 17 | PA0 | bidirectional | 5 V-tolerant (FT_a) I/O with analog switch function, additional functions ADC_IN0 and WKUP1, and alternate functions including SPI2_SCK, USART2_CTS/USART2_NSS, TIM16_CH1, TIM2_ETR/TIM2_CH1, USART1_TX and TIM1_CH1. |
| 18 | PA1 | bidirectional | 5 V-tolerant (FT_a) I/O with additional function ADC_IN1, and alternate functions including SPI1_SCK/I2S1_CK, USART2_RTS/USART2_DE/USART2_CK, TIM17_CH1, TIM2_CH2, USART1_RX, TIM1_CH2, I2C1_SMBA and EVENTOUT. |
| 19 | PA2 | bidirectional | 5 V-tolerant (FT_a) I/O with additional functions ADC_IN2, WKUP4 and LSCO, and alternate functions including SPI1_MOSI/I2S1_SD, USART2_TX, TIM16_CH1N, TIM3_ETR, TIM1_CH3 and TIM2_CH3. |
| 20 | PA3 | bidirectional | 5 V-tolerant (FT_a) I/O with additional function ADC_IN3, and alternate functions including SPI2_MISO, USART2_RX, TIM1_CH1N, TIM2_CH4, TIM1_CH4 and EVENTOUT. |
| 21 | PA4 | bidirectional | 5 V-tolerant (FT_a) I/O with additional functions ADC_IN4 and RTC_OUT2, and alternate functions including SPI1_NSS/I2S1_WS, USART2_TX, TIM1_CH2N, SPI2_MOSI, TIM14_CH1, TIM17_CH1N, USB_NOE and EVENTOUT. |
| 22 | PA5 | bidirectional | 5 V-tolerant (FT_a) I/O with additional function ADC_IN5, and alternate functions including SPI1_SCK/I2S1_CK, USART2_RX, TIM1_CH3N, TIM2_ETR/TIM2_CH1, TIM1_CH1 and EVENTOUT. |
| 23 | PA6 | bidirectional | 5 V-tolerant (FT_fa) I/O, Fm+ capable with analog switch, additional function ADC_IN6, and alternate functions including SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1 and I2C2_SDA. |
| 24 | PA7 | bidirectional | 5 V-tolerant (FT_fa) I/O, Fm+ capable with analog switch, additional function ADC_IN7, and alternate functions including SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1 and I2C2_SCL. |
| 25 | PC4 | bidirectional | 5 V-tolerant (FT_a) I/O with additional function ADC_IN11, and alternate functions USART1_TX and TIM2_ETR/TIM2_CH1. |
| 26 | PC5 | bidirectional | 5 V-tolerant (FT_a) I/O with additional functions ADC_IN12 and WKUP5, and alternate functions USART1_RX and TIM2_CH2. |
| 27 | PB0 | bidirectional | 5 V-tolerant (FT_a) I/O with additional function ADC_IN17, and alternate functions SPI1_NSS/I2S1_WS, TIM3_CH3 and TIM1_CH2N. |
| 28 | PB1 | bidirectional | 5 V-tolerant (FT_a) I/O with additional function ADC_IN18, and alternate functions TIM14_CH1, TIM3_CH4, TIM1_CH3N, TIM1_CH2N and EVENTOUT. |
| 29 | PB2 | bidirectional | 5 V-tolerant (FT_a) I/O with additional function ADC_IN19, and alternate functions USART1_RX, MCO2, SPI2_MISO and EVENTOUT. |
| 30 | PB10 | bidirectional | 5 V-tolerant (FT_fa) I/O, Fm+ capable with analog switch, additional function ADC_IN20, and alternate functions TIM2_CH3, SPI2_SCK and I2C2_SCL. |
| 31 | PB11 | bidirectional | 5 V-tolerant (FT_fa) I/O, Fm+ capable with analog switch, additional function ADC_IN21, and alternate functions SPI2_MOSI, TIM2_CH4 and I2C2_SDA. |
| 32 | PB12 | bidirectional | 5 V-tolerant (FT_a) I/O with additional function ADC_IN22, and alternate functions SPI2_NSS, TIM1_BKIN2, TIM1_BKIN and EVENTOUT. |
| 33 | PB13 | bidirectional | 5 V-tolerant (FT_sfa) I/O, Fm+ capable with analog switch, supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI2_SCK, TIM1_CH1N, I2C2_SCL and EVENTOUT. |
| 34 | PB14 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI2_MISO, TIM1_CH2N, I2C2_SDA and EVENTOUT. |
| 35 | PB15 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI2_MOSI, TIM1_CH3N and EVENTOUT, and additional function RTC_REFIN. |
| 36 | PA8 | bidirectional | 5 V-tolerant (FT_sa) I/O with analog switch, supplied only by VDDIO2 (internally connected to VDD on the GP package), additional function ADC_IN8, and alternate functions including MCO, USART2_TX, TIM1_CH1, SPI2_NSS, CRS_SYNC, TIM14_CH1 and USART1_RX. |
| 37 | PA9 | bidirectional | 5 V-tolerant (FT_sf) Fm+ capable I/O supplied by VDDIO2 (internally connected to VDD on the GP package), with alternate functions MCO, USART1_TX, TIM1_CH2, TIM3_ETR, SPI2_MISO, I2C1_SCL, EVENTOUT and I2C2_SCL; it can be remapped in place of PA11 via SYSCFG_CFGR1. |
| 38 | PC6 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_CH1 and TIM2_CH3. |
| 39 | PC7 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_CH2 and TIM2_CH4. |
| 40 | PD8 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate function SPI1_SCK/I2S1_CK. |
| 41 | PD9 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI1_NSS/I2S1_WS and TIM1_BKIN2. |
| 42 | PA10 | bidirectional | 5 V-tolerant (FT_sf) Fm+ capable I/O supplied by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI2_MOSI, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT and I2C2_SDA. |
| 43 | PA11 [PA9] | bidirectional | 5 V-tolerant (FT_usf) Fm+ capable I/O with USB function USB_DM, and alternate functions SPI1_MISO/I2S1_MCK, USART1_CTS/USART1_NSS, TIM1_CH4, TIM1_BKIN2 and I2C2_SCL; PA9 can be remapped in its place via SYSCFG_CFGR1. |
| 44 | PA12 [PA10] | bidirectional | 5 V-tolerant (FT_usf) Fm+ capable I/O with USB function USB_DP, and alternate functions SPI1_MOSI/I2S1_SD, USART1_RTS/USART1_DE/USART1_CK, TIM1_ETR, I2S_CKIN and I2C2_SDA; PA10 can be remapped in its place via SYSCFG_CFGR1. |
| 45 | PA13 | bidirectional | 5 V-tolerant (FT_sa) I/O with analog switch, configured as SWDIO after reset with internal pull-up enabled; additional function ADC_IN13, and alternate functions IR_OUT, USB_NOE, TIM3_ETR, USART2_RX and EVENTOUT. |
| 46 | PA14-BOOT0 | bidirectional | 5 V-tolerant (FT_sa) I/O with analog switch, configured as SWCLK after reset with internal pull-down enabled; additional functions ADC_IN14 and BOOT0, and alternate functions USART2_TX, EVENTOUT, SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, MCO2 and USART1_RTS/USART1_DE/USART1_CK. |
| 47 | PA15 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, MCO2, USART1_RTS/USART1_DE/USART1_CK, TIM2_ETR/TIM2_CH1, USB_NOE and EVENTOUT. |
| 48 | PC8 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_CH3 and TIM1_CH1. |
| 49 | PC9 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_CH4, TIM1_CH2, I2S_CKIN and USB_NOE. |
| 50 | PD0 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions EVENTOUT, TIM16_CH1 and SPI2_NSS. |
| 51 | PD1 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions EVENTOUT, TIM17_CH1 and SPI2_SCK. |
| 52 | PD2 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions TIM3_ETR and TIM1_CH1N. |
| 53 | PD3 | bidirectional | 5 V-tolerant (FT_s) I/O supplied only by VDDIO2 (internally connected to VDD on the GP package), with alternate functions USART2_CTS/USART2_NSS, TIM1_CH2N and SPI2_MISO. |
| 54 | PD4 | bidirectional | 5 V-tolerant (FT) I/O with alternate functions SPI2_MOSI, USART2_RTS/USART2_DE/USART2_CK and TIM1_CH3N. |
| 55 | PD5 | bidirectional | 5 V-tolerant (FT) I/O with alternate functions SPI1_MISO/I2S1_MCK, USART2_TX and TIM1_BKIN. |
| 56 | PD6 | bidirectional | 5 V-tolerant (FT) I/O with alternate functions SPI1_MOSI/I2S1_SD and USART2_RX. |
| 57 | PB3 | bidirectional | 5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions SPI1_SCK/I2S1_CK, TIM1_CH2, TIM3_CH2, USART1_RTS/USART1_DE/USART1_CK, I2C2_SCL, TIM2_CH2 and EVENTOUT. |
| 58 | PB4 | bidirectional | 5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS/USART1_NSS, TIM17_BKIN, I2C2_SDA and EVENTOUT. |
| 59 | PB5 | bidirectional | 5 V-tolerant (FT) I/O with additional function WKUP6, and alternate functions SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, TIM3_CH3 and I2C1_SMBA. |
| 60 | PB6 | bidirectional | 5 V-tolerant (FT_f) Fm+ capable I/O with additional function WKUP3, and alternate functions USART1_TX, TIM1_CH3, TIM16_CH1N, TIM3_CH3, SPI2_MISO, USART1_NSS/USART1_CTS, I2C1_SCL and I2C1_SMBA, among others. |
| 61 | PB7 | bidirectional | 5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions USART1_RX, TIM1_CH4, TIM17_CH1N, TIM3_CH4, SPI2_MOSI, I2C1_SDA, EVENTOUT, USART2_CTS/USART2_NSS, TIM16_CH1, TIM3_CH1 and I2C1_SCL. |
| 62 | PB8 | bidirectional | 5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions USART2_CTS/USART2_NSS, TIM16_CH1, TIM3_CH1, SPI2_SCK, I2C1_SCL and EVENTOUT. |
| 63 | PB9 | bidirectional | 5 V-tolerant (FT_f) Fm+ capable I/O with alternate functions IR_OUT, USART2_RTS/USART2_DE/USART2_CK, TIM17_CH1, TIM3_CH2, SPI2_NSS, I2C1_SDA and EVENTOUT. |
| 64 | PC10 | bidirectional | 5 V-tolerant (FT) I/O with alternate function TIM1_CH3. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMICROELECTRONICS |
| Package | LQFP-64(10x10) |
| Category | Global Sourcing Parts |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External supply voltage | VDD | -0.3 |  | 4 | V |  | 51 |
| External supply voltage for selected I/Os | VDDIO2 | -0.3 |  | 4 | V |  | 51 |
| External voltage on VREF+ pin | VREF+ | -0.3 |  |  | V |  | 51 |
| Input voltage on pin | VIN | -0.3 |  |  | V |  | 51 |
| Current into VDD/VDDA and VDDIO2 power pins (source) | IVDD/VDDA,VDDIO2 |  |  | 100 | mA |  | 51 |
| Current out of VSS/VSSA ground pin (sink) | IVSS/VSSA |  |  | 100 | mA |  | 51 |
| Output current sunk by any I/O and control pin | IIO(PIN) |  |  | 20 | mA | Output current sunk by any I/O and control pin | 51 |
| Output current sourced by any I/O and control pin | IIO(PIN) |  |  | 20 | mA | Output current sourced by any I/O and control pin | 51 |
| Total output current sunk by sum of all I/Os and control pins | ∑I(PIN) |  |  | 80 | mA | Total output current sunk by sum of all I/Os and control pins | 51 |
| Total output current sourced by sum of all I/Os and control pins | ∑I(PIN) |  |  | 80 | mA | Total output current sourced by sum of all I/Os and control pins | 51 |
| Injected current on a FT_xx pin (negative injection; positive not applicable) | IINJ(PIN) |  |  | -5 | mA | Injected current on a FT_xx pin; positive NA | 52 |
| Total injected current (sum of all I/Os and control pins) | ∑IINJ(PIN) |  |  | -25 | mA |  | 52 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 52 |
| Maximum junction temperature | TJ |  |  | 130 | °C |  | 52 |
| Standard operating voltage | VDD | 2 |  | 3.6 | V |  | 53 |
| External supply voltage for selected I/Os | VDDIO2 | 1.65 |  | 3.6 | V |  | 53 |
| I/O input voltage | VIN | -0.3 |  |  | V |  | 53 |
| AHB clock frequency | fHCLK |  |  | 48 | MHz |  | 53 |
| APB clock frequency | fPCLK |  |  | 48 | MHz |  | 53 |
| Ambient temperature (suffix 6) | TA | -40 |  | 85 | °C | Suffix 6 | 53 |
| Junction temperature (suffix 6) | TJ | -40 |  | 105 | °C | Suffix 6 | 53 |
| VDD rise time rate | tVDD | 0 |  |  | µs/V |  | 53 |
| VDD fall time rate | tVDD | 10 |  |  | µs/V |  | 53 |
| POR temporization when VDD crosses VPOR | tRSTTEMPO |  | 270 | 500 | µs | VDD rising | 54 |
| Power-on reset threshold | VPOR | 1.9 | 1.94 | 1.98 | V |  | 54 |
| Power-down reset threshold | VPDR | 1.88 | 1.92 | 1.96 | V |  | 54 |
| Brownout reset threshold 1 | VBOR1 | 2.05 | 2.1 | 2.18 | V | VDD rising | 54 |
| Brownout reset threshold 1 | VBOR1 | 1.95 | 2 | 2.08 | V | VDD falling | 54 |
| Brownout reset threshold 2 | VBOR2 | 2.2 | 2.31 | 2.38 | V | VDD rising | 54 |
| Brownout reset threshold 2 | VBOR2 | 2.1 | 2.21 | 2.28 | V | VDD falling | 54 |
| Brownout reset threshold 3 | VBOR3 | 2.5 | 2.62 | 2.68 | V | VDD rising | 54 |
| Brownout reset threshold 3 | VBOR3 | 2.4 | 2.52 | 2.58 | V | VDD falling | 54 |
| Brownout reset threshold 4 | VBOR4 | 2.8 | 2.91 | 3 | V | VDD rising | 54 |
| Brownout reset threshold 4 | VBOR4 | 2.7 | 2.81 | 2.9 | V | VDD falling | 54 |
| Internal reference voltage | VREFINT | 1.182 | 1.212 | 1.232 | V |  | 54 |
| Internal reference voltage spread over the temperature range | ∆VREFINT |  | 30 | 50 | mV | VDD = 3 V | 54 |
| Average temperature coefficient | TCoeff |  | 20 | 70 | ppm/°C |  | 54 |
| Long term stability | ACoeff |  | 300 | 1000 | ppm | 1000 hours, T = 25 °C | 54 |
| Voltage coefficient | VDDCoeff |  | 250 | 1200 | ppm/V | 3.0 V < VDD < 3.6 V | 54 |
| Weak pull-up equivalent resistor | RPU | 25 | 40 | 55 | kΩ | VIN = VSS | 79 |
| Weak pull-down equivalent resistor | RPD | 25 | 40 | 55 | kΩ | VIN = VDDIOx | 79 |
| Output low level voltage, CMOS port | VOL |  |  | 0.4 | V | /IIO/ = 8 mA, VDDIOx ≥ 2.7 V | 81 |
| Output high level voltage, TTL port | VOH | 2.4 |  |  | V |  | 81 |
| NRST weak pull-up equivalent resistor | RPU | 25 | 40 | 55 | kΩ | VIN = VSS | 83 |
| NRST input filtered pulse | VF(NRST) |  |  | 70 | ns | 2.0 V < VDD < 3.6 V | 83 |
| NRST input not filtered pulse | VNF(NRST) | 350 |  |  | ns | 2.0 V < VDD < 3.6 V | 83 |
| Analog supply voltage | VDDA | 2 |  | 3.6 | V |  | 84 |
| ADC clock frequency | fADC | 0.14 |  | 35 | MHz |  | 84 |
| Sampling rate, 12 bits | fs |  |  | 2.5 | MSps | 12 bits | 84 |
| HSI48 frequency | fHSI48 | 47.92 |  | 48.4 | MHz | VDD=3.0 V, TA=30 °C | 72 |
| HSI48 oscillator frequency drift over temperature and VDD full voltage range | ∆Temp(HSI) | -1 |  | 1 | % | TA= 0 to 85 °C | 72 |
| HSI48 oscillator frequency drift over temperature and VDD full voltage range | ∆Temp(HSI) | -2.5 |  | 2 | % | TA= -40 to 125 °C | 72 |
| HSIUSB48 frequency | fHSIUSB48 |  | 48 |  | MHz | VDD = 3.0 V, TA = 30 °C | 73 |
| HSIUSB48 oscillator accuracy over temperature (factory calibrated) | ACCHSIUSB48_REL | -3 |  | 3 | % | VDD = 3.0 V to 3.6 V, TA = -15 to 85 °C | 73 |
| HSIUSB48 oscillator accuracy over temperature (factory calibrated) | ACCHSIUSB48_REL | -4.5 |  | 4.5 | % | VDD = 2.0 V to 3.6 V, TA = -40 to 125 °C | 73 |
| LSI frequency | fLSI | 31.04 | 32 | 32.96 | kHz | VDD = 3.3 V, TA = 25 °C | 74 |
| LSI frequency | fLSI | 29.5 |  | 34 | kHz | VDD = 2 V to 3.6 V, TA = -40 to 125 °C | 74 |
| Endurance | NEND | 10 |  |  | kcycles | TJ = -40 to +130 °C | 75 |
| I/O pin capacitance | CIO |  | 5 |  | pF |  | 79 |
| NRST input Schmitt trigger voltage hysteresis | Vhys(NRST) |  | 200 |  | mV |  | 83 |

## CAD (KiCad official)

- Symbol: `STM32C071RBT6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `stm32c071rbt6-etched.step` / `stm32c071rbt6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32c071rbt6.step` / `stm32c071rbt6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMICROELECTRONICS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8556946164613337088) (129 pp, sha256 `47df10c3b7af4b1b`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32c071rbt6-datasheet.pdf)