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STM32C071CBT6

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by adom

ST(意法半导体) Global Sourcing Parts, LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32C071CBT6

ST(意法半导体) · Global Sourcing Parts · LQFP-48(7x7)

STM32C071CBT6 from ST(意法半导体), in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC13 bidirectional 5 V-tolerant (FT) I/O with alternate functions TIM1_ETR and TIM1_BKIN and additional functions RTC_TS, RTC_OUT1 and WKUP2.
2 PC14-OSCX_IN bidirectional 5 V-tolerant I/O with FT_f structure (Fm+ capable), serving as OSCX_IN with alternate functions including USART1_TX, TIM1_ETR, TIM1_BKIN2, IR_OUT, TIM17_CH1, TIM3_CH2, SPI2_NSS, I2C1_SDA and EVENTOUT.
3 PC15-OSCX_OUT bidirectional 5 V-tolerant (FT) I/O serving as OSCX_OUT, with alternate functions OSC32_EN, OSC_EN, TIM1_ETR and TIM3_CH3.
4 PF3 bidirectional 5 V-tolerant (FT) I/O with no alternate or additional functions listed in Table 12.
5 VREF+ power_in Positive reference voltage for the ADC, specified from 2 V up to VDD in Table 55.
6 VDD/VDDA power_in Main digital and analog supply pin; standard operating voltage VDD is 2.0 V to 3.6 V (Table 24).
7 VSS/VSSA power_in Ground pin for the digital and analog supply; all voltages are referenced to VSS.
8 PF0-OSC_IN bidirectional 5 V-tolerant (FT) I/O serving as OSC_IN, with alternate functions CRS_SYNC and TIM14_CH1.
9 PF1-OSC_OUT bidirectional 5 V-tolerant (FT) I/O serving as OSC_OUT, with alternate function OSC_EN.
10 PF2-NRST bidirectional Reset pin with embedded weak pull-up (RST structure) when configured as reset, becoming a 5 V-tolerant FT I/O when configured as GPIO; alternate functions MCO and TIM1_CH4.
11 PA0 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions include SPI2_SCK, USART2_CTS/USART2_NSS, TIM16_CH1, TIM2_CH1, USART1_TX and TIM1_CH1, additional functions ADC_IN0 and WKUP1.
12 PA1 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions include SPI1_SCK/I2S1_CK, USART2_RTS/USART2_DE/USART2_CK, TIM17_CH1, TIM2_CH2, USART1_RX, TIM1_CH2, I2C1_SMBA and EVENTOUT, additional function ADC_IN1.
13 PA2 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions include SPI1_MOSI/I2S1_SD, USART2_TX, TIM16_CH1N, TIM3_ETR, TIM1_CH3 and TIM2_CH3, additional functions ADC_IN2, WKUP4 and LSCO.
14 PA3 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions include SPI2_MISO, USART2_RX, TIM1_CH1N, TIM2_CH4, TIM1_CH4 and EVENTOUT, additional function ADC_IN3.
15 PA4 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions include SPI1_NSS/I2S1_WS, USART2_TX, TIM1_CH2N, SPI2_MOSI, TIM14_CH1, TIM17_CH1N, USB_NOE and EVENTOUT, additional functions ADC_IN4 and RTC_OUT2.
16 PA5 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions include SPI1_SCK/I2S1_CK, USART2_RX, TIM1_CH3N, TIM2_CH1, TIM1_CH1 and EVENTOUT, additional function ADC_IN5.
17 PA6 bidirectional 5 V-tolerant I/O with FT_fa structure (Fm+ capable, analog switch); alternate functions include SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1 and I2C2_SDA, additional function ADC_IN6.
18 PA7 bidirectional 5 V-tolerant I/O with FT_fa structure (Fm+ capable, analog switch); alternate functions include SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1 and I2C2_SCL, additional function ADC_IN7.
19 PB0 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions SPI1_NSS/I2S1_WS, TIM3_CH3 and TIM1_CH2N, additional function ADC_IN17.
20 PB1 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions include TIM14_CH1, TIM3_CH4, TIM1_CH3N, TIM1_CH2N and EVENTOUT, additional function ADC_IN18.
21 PB2 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions USART1_RX, MCO2, SPI2_MISO and EVENTOUT, additional function ADC_IN19.
22 PB10 bidirectional 5 V-tolerant I/O with FT_fa structure (Fm+ capable, analog switch); alternate functions TIM2_CH3, SPI2_SCK and I2C2_SCL, additional function ADC_IN20.
23 PB11 bidirectional 5 V-tolerant I/O with FT_fa structure (Fm+ capable, analog switch); alternate functions SPI2_MOSI, TIM2_CH4 and I2C2_SDA, additional function ADC_IN21.
24 PB12 bidirectional 5 V-tolerant I/O with analog switch (FT_a); alternate functions SPI2_NSS, TIM1_BKIN2, TIM1_BKIN and EVENTOUT, additional function ADC_IN22.
25 PB13 bidirectional 5 V-tolerant I/O with FT_sfa structure, supplied only by VDDIO2 (internally tied to VDD on GP packages), with alternate functions SPI2_SCK, TIM1_CH1N, I2C2_SCL and EVENTOUT.
26 PB14 bidirectional 5 V-tolerant I/O with FT_s structure, supplied only by VDDIO2; alternate functions SPI2_MISO, TIM1_CH2N, I2C2_SDA and EVENTOUT.
27 PB15 bidirectional 5 V-tolerant I/O with FT_s structure, supplied only by VDDIO2; alternate functions SPI2_MOSI, TIM1_CH3N and EVENTOUT, additional function RTC_REFIN.
28 PA8 bidirectional 5 V-tolerant I/O with analog switch (FT_sa), supplied by VDDIO2 structure per Table 11; alternate functions include MCO, USART2_TX, TIM1_CH1, SPI2_NSS, CRS_SYNC, SPI2_MISO, EVENTOUT and MCO2, additional function ADC_IN8.
29 PA9 bidirectional 5 V-tolerant I/O with FT_sf structure that can be remapped in place of PA11 via SYSCFG_CFGR1; alternate functions include MCO, USART1_TX, TIM1_CH2, TIM3_ETR, SPI2_MISO, I2C1_SCL, EVENTOUT and I2C2_SCL.
30 PC6 bidirectional 5 V-tolerant I/O with FT_s structure, supplied only by VDDIO2; alternate functions TIM3_CH1 and TIM2_CH3.
31 PC7 bidirectional 5 V-tolerant I/O with FT_s structure, supplied only by VDDIO2; alternate functions TIM3_CH2 and TIM2_CH4.
32 PA10 bidirectional 5 V-tolerant I/O with FT_sf structure that can be remapped in place of PA12 via SYSCFG_CFGR1; alternate functions SPI2_MOSI, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT and I2C2_SDA.
33 PA11 [PA9] bidirectional 5 V-tolerant USB-capable I/O (FT_usf) with default function PA11 and remap option to PA9; alternate functions SPI1_MISO/I2S1_MCK, USART1_CTS/USART1_NSS, TIM1_CH4, TIM1_BKIN2 and I2C2_SCL, additional function USB_DM.
34 PA12 [PA10] bidirectional 5 V-tolerant USB-capable I/O (FT_usf) with default function PA12 and remap option to PA10; alternate functions SPI1_MOSI/I2S1_SD, USART1_RTS/USART1_DE/USART1_CK, TIM1_ETR, I2S_CKIN and I2C2_SDA, additional function USB_DP.
35 PA13 bidirectional 5 V-tolerant I/O with analog switch (FT_sa) that is configured as SWDIO with internal pull-up after reset; alternate functions include IR_OUT, USB_NOE, TIM3_ETR, USART2_RX and EVENTOUT, additional function ADC_IN13.
36 PA14-BOOT0 bidirectional 5 V-tolerant I/O with analog switch (FT_sa) that is configured as SWCLK with internal pull-down after reset; alternate functions include USART2_TX, EVENTOUT, SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1 and MCO2, additional functions ADC_IN14 and BOOT0.
37 PA15 bidirectional 5 V-tolerant I/O with FT_s structure, supplied only by VDDIO2; alternate functions include SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, MCO2, TIM2_CH1, USB_NOE and EVENTOUT.
38 PD0 bidirectional 5 V-tolerant I/O with FT_s structure, supplied only by VDDIO2; alternate functions EVENTOUT, TIM16_CH1 and SPI2_NSS.
39 PD1 bidirectional 5 V-tolerant I/O with FT_s structure, supplied only by VDDIO2; alternate functions EVENTOUT, TIM17_CH1 and SPI2_SCK.
40 PD2 bidirectional 5 V-tolerant I/O with FT_s structure, supplied only by VDDIO2; alternate functions TIM3_ETR and TIM1_CH1N.
41 PD3 bidirectional 5 V-tolerant I/O with FT_s structure, supplied only by VDDIO2; alternate functions USART2_CTS/USART2_NSS, TIM1_CH2N and SPI2_MISO.
42 PB3 bidirectional 5 V-tolerant I/O with FT_f structure (Fm+ capable); alternate functions SPI1_SCK/I2S1_CK, TIM1_CH2, TIM3_CH2, USART1_RTS/USART1_DE/USART1_CK, I2C2_SCL, TIM2_CH2 and EVENTOUT.
43 PB4 bidirectional 5 V-tolerant I/O with FT_f structure (Fm+ capable); alternate functions SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS/USART1_NSS, TIM17_BKIN, I2C2_SDA and EVENTOUT.
44 PB5 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, TIM3_CH3 and I2C1_SMBA, additional function WKUP6.
45 PB6 bidirectional 5 V-tolerant I/O with FT_f structure (Fm+ capable); alternate functions include USART1_TX, TIM1_CH3, TIM16_CH1N, TIM3_CH3, SPI2_MISO, USART1_NSS/USART1_CTS, I2C1_SCL and I2C1_SMBA, additional function WKUP3.
46 PB7 bidirectional 5 V-tolerant I/O with FT_f structure (Fm+ capable); alternate functions include USART1_RX, TIM1_CH4, TIM17_CH1N, TIM3_CH4, SPI2_MOSI, I2C1_SDA, EVENTOUT and USART2_CTS/USART2_NSS.
47 PB8 bidirectional 5 V-tolerant I/O with FT_f structure (Fm+ capable); alternate functions USART2_CTS/USART2_NSS, TIM16_CH1, TIM3_CH1, SPI2_SCK, I2C1_SCL and EVENTOUT.
48 PB9 bidirectional 5 V-tolerant I/O with FT_f structure (Fm+ capable); alternate functions IR_OUT, USART2_RTS/USART2_DE/USART2_CK, TIM17_CH1, TIM3_CH2, SPI2_NSS, I2C1_SDA and EVENTOUT.

Key specifications

Parameter Value
Manufacturer ST(意法半导体)
Package LQFP-48(7x7)
Category Global Sourcing Parts
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External supply voltage VDD -0.3 4 V 51
External supply voltage for selected I/Os VDDIO2 -0.3 4 V 51
External voltage on VREF+ pin VREF+ -0.3 V 51
Input voltage on pin VIN -0.3 V 51
Current into VDD/VDDA and VDDIO2 power pins (source) IVDD/VDDA,VDDIO2 100 mA 51
Current out of VSS/VSSA ground pin (sink) IVSS/VSSA 100 mA 51
Output current sunk by any I/O and control pin IIO(PIN) 20 mA 51
Output current sourced by any I/O and control pin IIO(PIN) 20 mA 51
Total output current sunk by sum of all I/Os and control pins ∑I(PIN) 80 mA 51
Total output current sourced by sum of all I/Os and control pins ∑I(PIN) 80 mA 51
Injected current on a FT_xx pin IINJ(PIN) -5 mA 52
Total injected current (sum of all I/Os and control pins) ∑IINJ(PIN) -25 mA 52
Storage temperature range TSTG -65 150 °C 52
Maximum junction temperature TJ 130 °C 52
Standard operating voltage VDD 2 3.6 V 53
External supply voltage for selected I/Os VDDIO2 1.65 3.6 V 53
I/O input voltage VIN -0.3 V 53
AHB clock frequency fHCLK 48 MHz 53
APB clock frequency fPCLK 48 MHz 53
Ambient temperature (order code suffix 6) TA -40 85 °C Suffix 6 53
Junction temperature (order code suffix 6) TJ -40 105 °C Suffix 6 53
VDD rise time rate tVDD 0 µs/V 53
VDD fall time rate 10 µs/V 53
POR temporization when VDD crosses VPOR tRSTTEMPO 270 500 µs VDD rising 54
Power-on reset threshold VPOR 1.9 1.94 1.98 V 54
Power-down reset threshold VPDR 1.88 1.92 1.96 V 54
Brownout reset threshold 1 VBOR1 2.05 2.1 2.18 V VDD rising 54
Brownout reset threshold 1 VBOR1 1.95 2 2.08 V VDD falling 54
Brownout reset threshold 2 VBOR2 2.2 2.31 2.38 V VDD rising 54
Brownout reset threshold 2 VBOR2 2.1 2.21 2.28 V VDD falling 54
Brownout reset threshold 3 VBOR3 2.5 2.62 2.68 V VDD rising 54
Brownout reset threshold 3 VBOR3 2.4 2.52 2.58 V VDD falling 54
Brownout reset threshold 4 VBOR4 2.8 2.91 3 V VDD rising 54
Brownout reset threshold 4 VBOR4 2.7 2.81 2.9 V VDD falling 54
BOR consumption from VDD IDD(BOR) 2.2 2.5 µA 54
Internal reference voltage VREFINT 1.182 1.212 1.232 V 54
Start time of reference voltage buffer when ADC is enabled tstart_vrefint 8 12 µs 54
Internal reference voltage spread over the temperature range ∆VREFINT 30 50 mV VDD = 3 V 54
Average temperature coefficient TCoeff 20 70 ppm/°C 54
Long term stability ACoeff 300 1000 ppm 1000 hours, T = 25 °C 54
Voltage coefficient VDDCoeff 250 1200 ppm/V 3.0 V < VDD < 3.6 V 54
Supply current in Run mode, flash memory, 25 °C IDD(Run) 3.7 4 mA fHCLK 48 MHz, fetch from flash, 25 °C; typ at VDD 3.0 V, max at 3.6 V 56
Supply current in Run mode, flash memory, 125 °C IDD(Run) 4.2 5 mA fHCLK 48 MHz, fetch from flash, 125 °C; typ at VDD 3.0 V, max at 3.6 V 56
Supply current in Run mode, SRAM, 25 °C IDD(Run) 3.1 3.4 mA fHCLK 48 MHz, fetch from SRAM, 25 °C; typ at VDD 3.0 V, max at 3.6 V 57
Supply current in Sleep mode, flash enabled, 25 °C IDD(Sleep) 0.77 0.97 mA fHCLK 48 MHz, all peripherals disabled, 25 °C; typ at VDD 3.0 V, max at 3.6 V 61
Supply current in Sleep mode, flash enabled, 125 °C IDD(Sleep) 1.2 2.1 mA fHCLK 48 MHz, all peripherals disabled, 125 °C; typ at VDD 3.0 V, max at 3.6 V 61
Supply current in Stop mode, all clocks off, 25 °C IDD(Stop) 87.5 120 µA All clocks off, VDD 3.6 V, 25 °C 63
Supply current in Stop mode, all clocks off, 125 °C IDD(Stop) 495 1200 µA All clocks off, VDD 3.6 V, 125 °C 63
Supply current in Standby mode, all clocks off, 25 °C IDD(Standby) 7.75 9.5 µA All clocks off, VDD 3.6 V, 25 °C 64
Supply current in Shutdown mode, all clocks off, 25 °C IDD(Shutdown) 41 130 nA All clocks off, VDD 3.6 V, 25 °C 64
Wake-up time from Sleep to Run mode, flash powered during Sleep tWUSLEEP 10 12 CPU clock cycles HCLK = HSI48/4 = 12 MHz 68
Wake-up time from Sleep to Run mode, flash not powered during Sleep tWUSLEEP 4.74 5.02 µs HCLK = HSI48/4 = 12 MHz 68
Wake-up time from Stop mode, flash powered during Stop tWULPSTOP 2.7 3.1 µs Clock after wake-up HCLK = HSI48/4 = 12 MHz 68
Wake-up time from Stop mode, flash not powered during Stop tWULPSTOP 5.9 6.4 µs Clock after wake-up HCLK = HSI48/4 = 12 MHz 68
Wake-up time from Standby mode tWUSTBY 23 35 µs Clock after wake-up HCLK = HSI48/4 = 12 MHz 68
Wake-up time from Shutdown mode tWUSHDN 385 466 µs Clock after wake-up HCLK = HSI48/4 = 12 MHz 68
Oscillator frequency (HSE crystal/ceramic) fOSC_IN 4 48 MHz 70
HSI48 frequency fHSI48 47.92 48.4 MHz VDD = 3.0 V, TA = 30 °C 72
ADC power supply voltage VDDA 2 3.6 V 84
ADC clock frequency fADC 0.14 35 MHz 84
Sampling rate, 12-bit resolution fs 2.5 MSps 12 bits 84

CAD (KiCad official)

  • Symbol: STM32C071CBT6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32c071cbt6-etched.step / stm32c071cbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32c071cbt6.step / stm32c071cbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ST(意法半导体) datasheet (129 pp, sha256 47df10c3b7af4b1b, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF