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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32C031C6U6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)

STM32C031C6U6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PC13	bidirectional	5 V-tolerant I/O (FT) with default function PC13; alternate functions TIM1_ETR and TIM1_BKIN; additional functions RTC_TS, RTC_OUT1 and WKUP2.
2	PC14-OSCX_IN	bidirectional	5 V-tolerant I/O (FT) with default function PC14; alternate functions include USART1_TX, TIM1_ETR and I2C1_SDA; additional function OSCX_IN.
3	PC15-OSCX_OUT	bidirectional	5 V-tolerant I/O (FT) with default function PC15; alternate functions OSC32_EN, OSC_EN, TIM1_ETR and TIM3_CH3; additional function OSCX_OUT.
4	PF3	power_in	Listed as supply-type pin S in Table 12 with no alternate or additional function assigned.
5	VREF+	power_in	Positive ADC reference voltage; VREF+ conversion range is 2 V up to VDD according to Table 54.
6	VDD/VDDA	power_in	Power supply pin for VDD and VDDA; standard operating voltage is 2.0 V to 3.6 V (Table 24).
7	VSS/VSSA	power_in	Ground reference pin for VSS and VSSA; all voltages are referenced to VSS.
8	PF0-OSC_IN	bidirectional	5 V-tolerant I/O (FT) with default function PF0; alternate function TIM14_CH1; additional function OSC_IN.
9	PF1-OSC_OUT	bidirectional	5 V-tolerant I/O (FT) with default function PF1; alternate function OSC_EN; additional function OSC_OUT.
10	PF2-NRST	bidirectional	Bidirectional reset pin with embedded weak pull-up resistor; alternate functions MCO and TIM1_CH4.
11	PA0	bidirectional	5 V-tolerant I/O (FT) with default function PA0; alternate functions USART2_CTS, TIM16_CH1, USART1_TX and TIM1_CH1; additional function ADC_IN0 and WKUP1.
12	PA1	bidirectional	5 V-tolerant I/O (FT) with default function PA1; alternate functions include SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK and USART1_RX; additional function ADC_IN1.
13	PA2	bidirectional	5 V-tolerant I/O (FT) with default function PA2; alternate functions include SPI1_MOSI/I2S1_SD, USART2_TX and TIM16_CH1N; additional functions ADC_IN2, WKUP4 and LSCO.
14	PA3	bidirectional	5 V-tolerant I/O (FT) with default function PA3; alternate functions USART2_RX, TIM1_CH1N, TIM1_CH4 and EVENTOUT; additional function ADC_IN3.
15	PA4	bidirectional	5 V-tolerant I/O (FT) with default function PA4; alternate functions include SPI1_NSS/I2S1_WS, USART2_TX and TIM14_CH1; additional functions ADC_IN4, RTC_TS, RTC_OUT1 and WKUP2.
16	PA5	bidirectional	5 V-tolerant I/O (FT) with default function PA5; alternate functions include SPI1_SCK/I2S1_CK, USART2_RX and TIM1_CH1; additional function ADC_IN5.
17	PA6	bidirectional	5 V-tolerant I/O (FT) with default function PA6; alternate functions include SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN and TIM16_CH1; additional function ADC_IN6.
18	PA7	bidirectional	5 V-tolerant I/O (FT) with default function PA7; alternate functions include SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N and TIM14_CH1; additional function ADC_IN7.
19	PB0	bidirectional	5 V-tolerant I/O (FT) with default function PB0; alternate functions SPI1_NSS/I2S1_WS, TIM3_CH3 and TIM1_CH2N; additional function ADC_IN17.
20	PB1	bidirectional	5 V-tolerant I/O (FT) with default function PB1; alternate functions include TIM14_CH1, TIM3_CH4, TIM1_CH3N and EVENTOUT; additional function ADC_IN18.
21	PB2	bidirectional	5 V-tolerant I/O (FT) with default function PB2; alternate functions USART1_RX, MCO2 and EVENTOUT; additional function ADC_IN19.
22	PB10	bidirectional	5 V-tolerant I/O (FT) with default function PB10 and no listed alternate function; additional function ADC_IN20.
23	PB11	bidirectional	5 V-tolerant I/O (FT) with default function PB11 and no listed alternate function; additional function ADC_IN21.
24	PB12	bidirectional	5 V-tolerant I/O (FT) with default function PB12; alternate functions TIM1_BKIN2, TIM1_BKIN and EVENTOUT; additional function ADC_IN22.
25	PB13	bidirectional	5 V-tolerant I/O (FT) with default function PB13; alternate functions TIM1_CH1N and EVENTOUT.
26	PB14	bidirectional	5 V-tolerant I/O (FT) with default function PB14; alternate functions TIM1_CH2N and EVENTOUT.
27	PB15	bidirectional	5 V-tolerant I/O (FT) with default function PB15; alternate functions TIM1_CH3N and EVENTOUT; additional function RTC_REFIN.
28	PA8	bidirectional	5 V-tolerant I/O (FT) with default function PA8; alternate functions include MCO, USART2_TX, TIM1_CH1 and SPI1_NSS/I2S1_WS; additional function ADC_IN8.
29	PA9	bidirectional	5 V-tolerant I/O (FT) with default function PA9 (footnote 1: PA9 and PA10 can be remapped in place of PA11 and PA12); alternate functions MCO, USART1_TX, TIM1_CH2, TIM3_ETR, I2C1_SCL and EVENTOUT.
30	PC6	bidirectional	5 V-tolerant I/O (FT) with default function PC6; alternate function TIM3_CH1.
31	PC7	bidirectional	5 V-tolerant I/O (FT) with default function PC7; alternate function TIM3_CH2.
32	PA10	bidirectional	5 V-tolerant I/O (FT) with default function PA10 (footnote 1: remappable in place of PA12); alternate functions USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA and EVENTOUT.
33	PA11 [PA9]	bidirectional	5 V-tolerant I/O (FT) with default function PA11, remappable to PA9 (footnote 1); alternate functions include SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4 and TIM1_BKIN2; additional function ADC_IN11.
34	PA12 [PA10]	bidirectional	5 V-tolerant I/O (FT) with default function PA12, remappable to PA10 (footnote 1); alternate functions include SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR and I2S_CKIN; additional function ADC_IN12.
35	PA13	bidirectional	5 V-tolerant I/O (FT) with default function PA13 that is configured as SWDIO after reset with internal pull-up (footnote 2); alternate functions include IR_OUT, TIM3_ETR and USART2_RX; additional function ADC_IN13.
36	PA14-BOOT0	bidirectional	5 V-tolerant I/O (FT) with default function PA14 that is configured as SWCLK after reset with internal pull-down (footnote 2); additional functions ADC_IN14 and BOOT0.
37	PA15	bidirectional	5 V-tolerant I/O (FT) with default function PA15; alternate functions include SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, MCO2 and EVENTOUT.
38	PD0	bidirectional	5 V-tolerant I/O (FT) with default function PD0; alternate functions EVENTOUT and TIM16_CH1.
39	PD1	bidirectional	5 V-tolerant I/O (FT) with default function PD1; alternate functions EVENTOUT and TIM17_CH1.
40	PD2	bidirectional	5 V-tolerant I/O (FT) with default function PD2; alternate functions TIM3_ETR and TIM1_CH1N.
41	PD3	bidirectional	5 V-tolerant I/O (FT) with default function PD3; alternate functions USART2_CTS and TIM1_CH2N.
42	PB3	bidirectional	5 V-tolerant I/O (FT) with default function PB3; alternate functions include SPI1_SCK/I2S1_CK, TIM1_CH2, TIM3_CH2, USART1_RTS_DE_CK and EVENTOUT.
43	PB4	bidirectional	5 V-tolerant I/O (FT) with default function PB4; alternate functions include SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN and EVENTOUT.
44	PB5	bidirectional	5 V-tolerant I/O (FT) with default function PB5; alternate functions include SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, TIM3_CH3 and I2C1_SMBA; additional function WKUP6.
45	PB6	bidirectional	5 V-tolerant I/O (FT) with default function PB6; alternate functions include USART1_TX, TIM1_CH3, TIM16_CH1N, I2C1_SCL and I2C1_SMBA; additional function WKUP3.
46	PB7	bidirectional	5 V-tolerant I/O (FT) with default function PB7; alternate functions include USART1_RX, TIM1_CH4, TIM17_CH1N, TIM3_CH4, I2C1_SDA and EVENTOUT.
47	PB8	bidirectional	5 V-tolerant I/O (FT) with default function PB8; alternate functions include USART2_CTS, TIM16_CH1, TIM3_CH1, I2C1_SCL and EVENTOUT.
48	PB9	bidirectional	5 V-tolerant I/O (FT) with default function PB9; alternate functions include IR_OUT, USART2_RTS_DE_CK, TIM17_CH1, TIM3_CH2, I2C1_SDA and EVENTOUT.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	UFQFPN-48(7x7)
Category	Embedded Processors & Controllers
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDD - VSS external supply voltage	VDD-VSS	-0.3		4	V		42
Total output current sunk by sum of all I/Os and control pins	∑I(PIN)			80	mA		42
Total output current sourced by sum of all I/Os and control pins	∑I(PIN)			80	mA		42
Current into VDD/VDDA power pin (source)	IVDD/VDDA			100	mA		42
Current out of VSS/VSSA ground pin (sink)	IVSS/VSSA			100	mA		42
Output current sunk by any I/O and control pin	IIO(PIN)			20	mA		42
Output current sourced by any I/O and control pin	IIO(PIN)			20	mA		42
Injected current on a FT_xx pin	IINJ(PIN)	-5		0	mA		42
Storage temperature range	TSTG	-65		150	°C		43
Maximum junction temperature	TJ			130	°C		43
Standard operating voltage	VDD	2		3.6	V		44
I/O input voltage	VIN	-0.3			V		44
APB clock frequency	fPCLK			48	MHz		44
Ambient temperature (suffix 6)	TA	-40		85	°C	Suffix 6	44
Junction temperature (suffix 6)	TJ	-40		105	°C	Suffix 6	44
VDD rise time rate	tVDD	0			µs/V		44
VDD fall time rate	tVDD	10			µs/V		44
POR temporization when VDD crosses VPOR	tRSTTEMPO		270	500	µs	VDD rising	44
Power-on reset threshold	VPOR	1.9	1.94	1.98	V		44
Power-down reset threshold	VPDR	1.88	1.92	1.96	V		44
Internal reference voltage	VREFINT	1.182	1.212	1.232	V		45
Average temperature coefficient	TCoeff		20	70	ppm/°C		45
Long term stability	ACoeff		300	1000	ppm	1000 hours, T = 25 °C	45
Voltage coefficient	VDDCoeff		250	1200	ppm/V	3.0 V < VDD < 3.6 V	45
Supply current in Run mode from flash, 48 MHz, 85 °C	IDD(Run)		3.15	3.8	mA	fHCLK 48 MHz flash, all peripherals disabled; typ at VDD=3.0 V, max at VDD=3.6 V	47
Supply current in Stop mode, all clocks off, 85 °C	IDD(Stop)		125	350	µA	All clocks off, VDD=2 V	52
Supply current in Standby mode, all clocks off, 85 °C	IDD(Standby)		7.7	8.9	µA	All clocks off, VDD=2 V	53
Supply current in Standby mode, all clocks off, 85 °C	IDD(Standby)		8.95	11	µA	All clocks off, VDD=3.6 V	53
Supply current in Shutdown mode, all clocks off, 85 °C	IDD(Shutdown)		290	920	nA	All clocks off, VDD=2 V	53
Supply current in Shutdown mode, all clocks off, 85 °C	IDD(Shutdown)		460	1400	nA	All clocks off, VDD=3.6 V	53
User external clock source frequency (HSE)	fHSE_ext			48	MHz		57
Low-speed user external clock source frequency	fLSE_ext			1000	kHz		57
Oscillator frequency (HSE)	fOSC_IN	4		48	MHz		58
HSE feedback resistor	RF		200		kΩ		58
HSI48 frequency	fHSI48	47.92		48.4	MHz	VDD=3.0 V, TA=30 °C	61
HSI48 oscillator frequency drift over temperature (0 to 85 °C)	∆Temp(HSI)	-1		1	%	TA= 0 to 85 °C	61
LSI frequency	fLSI	31.04	32	32.96	kHz	VDD = 3.3 V, TA = 25 °C	62
LSI frequency	fLSI	29.5		34	kHz	VDD = 2 V to 3.6 V, TA = -40 to 125 °C	62
Endurance	NEND	10			kcycles	TJ = -40 to +130 °C	63
Data retention	tRET	30			Years	1 kcycle at TA = 85 °C	63
I/O input hysteresis	Vhys		200		mV		67
Weak pull-up equivalent resistor	RPU	25	40	55	kΩ	VIN = VSS	67
Weak pull-down equivalent resistor	RPD	25	40	55	kΩ	VIN = VDDIO1	67
I/O pin capacitance	CIO		5		pF		67
Output low level voltage CMOS port	VOL			0.4	V	/IIO/ = 8 mA, 2.7 V ≤ VDD ≤ 3.6 V	69
Output low level voltage all I/Os	VOL			1.3	V	/IIO/ = 20 mA, 2.7 V ≤ VDD ≤ 3.6 V	69
Output low level voltage all I/Os	VOL			0.45	V	/IIO/ = 4 mA, 2.7 V ≤ VDD ≤ 3.6 V	69
ADC supply voltage	VDDA	2		3.6	V		72
ADC clock frequency	fADC	0.14		35	MHz		72
Sampling rate 12 bits	fs			2.5	MSps	12 bits	72
External input impedance	RAIN			50	kΩ		72
Internal sample and hold capacitor	CADC		5		pF		72
VSENSE linearity with temperature	TL	-5	1	5	°C		77
Average slope from VSENSE voltage	Avg_Slope	2.4	2.53	2.65	mV/°C		77
Voltage at 30°C (±5 °C)	V30	0.742	0.76	0.786	V	Measured at VDDA = 3.3 V ±10 mV	77

CAD (KiCad official)

Symbol: STM32C031C6U6
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
3D model files: stm32c031c6u6-etched.step / stm32c031c6u6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32c031c6u6.step / stm32c031c6u6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (108 pp, sha256 c0de50247b672919, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

STM32C031C6U6

Verified STM32C031C6U6

Verification log 1 record

STM32C031C6U6

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance