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STM32C031C4U6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)

STM32C031C4U6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC13 bidirectional 5 V-tolerant I/O with alternate functions TIM1_ETR and TIM1_BKIN, and additional functions RTC_TS, RTC_OUT1 and WKUP2.
2 PC14-OSCX_IN bidirectional 5 V-tolerant I/O (PC14 at reset) that is also the OSCX_IN oscillator input, with alternate functions USART1_TX, TIM1_ETR, TIM1_BKIN2, IR_OUT, USART2_RTS_DE_CK, TIM17_CH1, TIM3_CH2, I2C1_SDA and EVENTOUT.
3 PC15-OSCX_OUT bidirectional 5 V-tolerant I/O (PC15 at reset) that is also the OSCX_OUT oscillator output, with alternate functions OSC32_EN, OSC_EN, TIM1_ETR and TIM3_CH3.
4 PF3 power_in Listed as supply (S) pin type with no alternate or additional functions.
5 VREF+ power_in Positive ADC reference voltage input, supply pin; ADC VREF+ range is 2 V to VDD.
6 VDD/VDDA power_in Digital and analog supply, 2.0 V to 3.6 V, to be decoupled with 100 nF plus 4.7 uF ceramic capacitors placed close to the pin.
7 VSS/VSSA power_in Digital and analog ground, supply pin, decoupled together with VDD/VDDA.
8 PF0-OSC_IN bidirectional 5 V-tolerant I/O (PF0 at reset) that is also OSC_IN, with alternate function TIM14_CH1.
9 PF1-OSC_OUT bidirectional 5 V-tolerant I/O (PF1 at reset) that is also OSC_OUT, with alternate function OSC_EN.
10 PF2-NRST bidirectional Bidirectional reset pin with embedded weak pull-up (NRST), 5 V-tolerant I/O with alternate functions MCO and TIM1_CH4.
11 PA0 bidirectional 5 V-tolerant I/O with alternate functions USART2_CTS, TIM16_CH1, USART1_TX and TIM1_CH1, and additional functions ADC_IN0 and WKUP1.
12 PA1 bidirectional 5 V-tolerant I/O with SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM17_CH1, USART1_RX, TIM1_CH2, I2C1_SMBA and EVENTOUT, plus ADC_IN1.
13 PA2 bidirectional 5 V-tolerant I/O with SPI1_MOSI/I2S1_SD, USART2_TX, TIM16_CH1N, TIM3_ETR and TIM1_CH3, plus ADC_IN2, WKUP4 and LSCO.
14 PA3 bidirectional 5 V-tolerant I/O with USART2_RX, TIM1_CH1N, TIM1_CH4 and EVENTOUT, plus ADC_IN3.
15 PA4 bidirectional 5 V-tolerant I/O with SPI1_NSS/I2S1_WS, USART2_TX, TIM1_CH2N, TIM14_CH1, TIM17_CH1N and EVENTOUT, plus ADC_IN4 and RTC_OUT2.
16 PA5 bidirectional 5 V-tolerant I/O with SPI1_SCK/I2S1_CK, USART2_RX, TIM1_CH3N, TIM1_CH1 and EVENTOUT, plus ADC_IN5.
17 PA6 bidirectional 5 V-tolerant I/O with SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN and TIM16_CH1, plus ADC_IN6.
18 PA7 bidirectional 5 V-tolerant I/O with SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1 and TIM17_CH1, plus ADC_IN7.
19 PB0 bidirectional 5 V-tolerant I/O with SPI1_NSS/I2S1_WS, TIM3_CH3 and TIM1_CH2N, plus ADC_IN17.
20 PB1 bidirectional 5 V-tolerant I/O with TIM14_CH1, TIM3_CH4, TIM1_CH3N, TIM1_CH2N and EVENTOUT, plus ADC_IN18.
21 PB2 bidirectional 5 V-tolerant I/O with USART1_RX, MCO2 and EVENTOUT, plus ADC_IN19.
22 PB10 bidirectional 5 V-tolerant I/O with no alternate functions, additional function ADC_IN20.
23 PB11 bidirectional 5 V-tolerant I/O with no alternate functions, additional function ADC_IN21.
24 PB12 bidirectional 5 V-tolerant I/O with TIM1_BKIN2, TIM1_BKIN and EVENTOUT, plus ADC_IN22.
25 PB13 bidirectional 5 V-tolerant I/O with TIM1_CH1N and EVENTOUT.
26 PB14 bidirectional 5 V-tolerant I/O with TIM1_CH2N and EVENTOUT.
27 PB15 bidirectional 5 V-tolerant I/O with TIM1_CH3N and EVENTOUT, plus additional function RTC_REFIN.
28 PA8 bidirectional 5 V-tolerant I/O with MCO, USART2_TX, TIM1_CH1, EVENTOUT, SPI1_NSS/I2S1_WS, TIM1_CH2N, TIM1_CH3N, TIM3_CH3, TIM3_CH4, TIM14_CH1, USART1_RX and MCO2, plus ADC_IN8.
29 PA9 bidirectional 5 V-tolerant I/O with MCO, USART1_TX, TIM1_CH2, TIM3_ETR, I2C1_SCL and EVENTOUT; can be remapped in place of PA11 via SYSCFG_CFGR1.
30 PC6 bidirectional 5 V-tolerant I/O with alternate function TIM3_CH1.
31 PC7 bidirectional 5 V-tolerant I/O with alternate function TIM3_CH2.
32 PA10 bidirectional 5 V-tolerant I/O with USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA and EVENTOUT; can be remapped in place of PA12 via SYSCFG_CFGR1.
33 PA11 [PA9] bidirectional 5 V-tolerant I/O with SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4 and TIM1_BKIN2, plus ADC_IN11; PA9 can be remapped here via SYSCFG_CFGR1.
34 PA12 [PA10] bidirectional 5 V-tolerant I/O with SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR and I2S_CKIN, plus ADC_IN12; PA10 can be remapped here via SYSCFG_CFGR1.
35 PA13 bidirectional 5 V-tolerant I/O, SWDIO at reset with internal pull-up activated, with IR_OUT, TIM3_ETR, USART2_RX and EVENTOUT, plus ADC_IN13.
36 PA14-BOOT0 bidirectional 5 V-tolerant I/O, SWCLK at reset with internal pull-down activated, also BOOT0, with USART2_TX, EVENTOUT, SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, MCO2 and USART1_RTS_DE_CK, plus ADC_IN14.
37 PA15 bidirectional 5 V-tolerant I/O with SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, MCO2, USART1_RTS_DE_CK and EVENTOUT.
38 PD0 bidirectional 5 V-tolerant I/O with EVENTOUT and TIM16_CH1.
39 PD1 bidirectional 5 V-tolerant I/O with EVENTOUT and TIM17_CH1.
40 PD2 bidirectional 5 V-tolerant I/O with TIM3_ETR and TIM1_CH1N.
41 PD3 bidirectional 5 V-tolerant I/O with USART2_CTS and TIM1_CH2N.
42 PB3 bidirectional 5 V-tolerant I/O with SPI1_SCK/I2S1_CK, TIM1_CH2, TIM3_CH2, USART1_RTS_DE_CK and EVENTOUT.
43 PB4 bidirectional 5 V-tolerant I/O with SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN and EVENTOUT.
44 PB5 bidirectional 5 V-tolerant I/O with SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, TIM3_CH3 and I2C1_SMBA, plus WKUP6.
45 PB6 bidirectional 5 V-tolerant I/O with USART1_TX, TIM1_CH3, TIM16_CH1N, TIM3_CH3, USART1_RTS_DE_CK, USART1_CTS, I2C1_SCL, I2C1_SMBA, SPI1 signals, TIM1_CH2, TIM3_CH1, TIM3_CH2, TIM16_BKIN and TIM17_BKIN, plus WKUP3.
46 PB7 bidirectional 5 V-tolerant I/O with USART1_RX, TIM1_CH4, TIM17_CH1N, TIM3_CH4, I2C1_SDA, EVENTOUT, USART2_CTS, TIM16_CH1, TIM3_CH1 and I2C1_SCL.
47 PB8 bidirectional 5 V-tolerant I/O with USART2_CTS, TIM16_CH1, TIM3_CH1, I2C1_SCL and EVENTOUT.
48 PB9 bidirectional 5 V-tolerant I/O with IR_OUT, USART2_RTS_DE_CK, TIM17_CH1, TIM3_CH2, I2C1_SDA and EVENTOUT.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-48(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: STM32C031C4U6
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32c031c4u6-etched.step / stm32c031c4u6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32c031c4u6.step / stm32c031c4u6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (108 pp, sha256 c0de50247b672919, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF