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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM32C011F6U6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-20(3x3)

STM32C011F6U6TR from STMicroelectronics, in a UFQFPN-20(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PC15-OSCX_OUT	bidirectional	5 V-tolerant I/O (PC15), default GPIO on reset; usable as OSCX_OUT (32.768 kHz LSE crystal oscillator output); alternate functions OSC32_EN, OSC_EN, TIM1_ETR, TIM3_CH3.
2	VDD/VDDA	power_in	External supply input, 2.0 V (1.96 V min once POR released) to 3.6 V, feeding the internal digital regulator, system analog (reset/clock) circuitry and the ADC analog supply (VDDA); also internally provides VDDIO1 and VREF+.
3	VSS/VSSA	power_in	Ground reference pin for the digital core and the analog (ADC) circuitry.
4	PF2-NRST	bidirectional	Bidirectional reset pin with an embedded weak pull-up resistor (RPU ~40 kΩ); also usable as GPIO PF2 with alternate functions MCO and TIM1_CH4.
5	PA0	bidirectional	5 V-tolerant I/O (PA0); alternate functions USART2_CTS, TIM16_CH1, USART1_TX, TIM1_CH1; additional functions ADC_IN0 and WKUP1 (Standby/Shutdown wakeup pin).
6	PA1	bidirectional	5 V-tolerant I/O (PA1); alternate functions SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM17_CH1, USART1_RX, TIM1_CH2, I2C1_SMBA, EVENTOUT; additional function ADC_IN1.
7	PA2	bidirectional	5 V-tolerant I/O (PA2); alternate functions SPI1_MOSI/I2S1_SD, USART2_TX, TIM16_CH1N, TIM3_ETR, TIM1_CH3; additional functions ADC_IN2, WKUP4 and LSCO (low-speed clock output).
8	PA3	bidirectional	5 V-tolerant I/O (PA3); alternate functions USART2_RX, TIM1_CH1N, TIM1_CH4, EVENTOUT; additional function ADC_IN3.
9	PA4	bidirectional	5 V-tolerant I/O (PA4); alternate functions SPI1_NSS/I2S1_WS, USART2_TX, TIM1_CH2N, TIM14_CH1, TIM17_CH1N, EVENTOUT; additional functions ADC_IN4, RTC_TS, RTC_OUT1 and WKUP2.
10	PA5	bidirectional	5 V-tolerant I/O (PA5); alternate functions SPI1_SCK/I2S1_CK, USART2_RX, TIM1_CH3N, TIM1_CH1, EVENTOUT; additional function ADC_IN5.
11	PA6	bidirectional	5 V-tolerant I/O (PA6); alternate functions SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1; additional function ADC_IN6.
12	PA7	bidirectional	5 V-tolerant I/O (PA7); alternate functions SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1; additional function ADC_IN7.
13	PA8	bidirectional	5 V-tolerant I/O (PA8); alternate functions MCO, USART2_TX, TIM1_CH1, EVENTOUT, SPI1_NSS/I2S1_WS, TIM1_CH2N, TIM1_CH3N, TIM3_CH3, TIM3_CH4, TIM14_CH1, USART1_RX, MCO2; additional function ADC_IN8.
14	PA11 [PA9]	bidirectional	5 V-tolerant I/O, default function PA11; can be remapped to carry the PA9 function in place of pins PA11/PA12 via SYSCFG_CFGR1 register; alternate functions SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2; additional function ADC_IN11.
15	PA12 [PA10]	bidirectional	5 V-tolerant I/O, default function PA12; can be remapped to carry the PA10 function in place of pins PA11/PA12 via SYSCFG_CFGR1 register; alternate functions SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN; additional function ADC_IN12.
16	PA13	bidirectional	5 V-tolerant I/O (PA13); upon reset configured as SWDIO alternate function with internal pull-up activated; other alternate functions IR_OUT, TIM3_ETR, USART2_RX, EVENTOUT; additional function ADC_IN13.
17	PA14-BOOT0	bidirectional	5 V-tolerant I/O (PA14); upon reset configured as SWCLK alternate function with internal pull-down activated; doubles as BOOT0 boot-mode selection input; other alternate functions USART2_TX, EVENTOUT, SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, MCO2, USART1_RTS_DE_CK; additional functions ADC_IN14, BOOT0.
18	PB6	bidirectional	5 V-tolerant I/O (PB6); alternate functions USART1_TX, TIM1_CH3, TIM16_CH1N, TIM3_CH3, USART1_RTS_DE_CK, USART1_CTS, I2C1_SCL, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI1_MISO/I2S1_MCK, SPI1_SCK/I2S1_CK, TIM1_CH2, TIM3_CH1, TIM3_CH2, TIM16_BKIN, TIM17_BKIN; additional function WKUP3.
19	PB7	bidirectional	5 V-tolerant I/O (PB7); alternate functions USART1_RX, TIM1_CH4, TIM17_CH1N, TIM3_CH4, I2C1_SDA, EVENTOUT, USART2_CTS, TIM16_CH1, TIM3_CH1, I2C1_SCL; additional function RTC_REFIN.
20	PC14-OSCX_IN	bidirectional	5 V-tolerant I/O (PC14), default GPIO on reset; usable as OSCX_IN (32.768 kHz LSE crystal oscillator input); alternate functions USART1_TX, TIM1_ETR, TIM1_BKIN2, IR_OUT, USART2_RTS_DE_CK, TIM17_CH1, TIM3_CH2, I2C1_SDA, EVENTOUT.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	UFQFPN-20(3x3)
Category	Embedded Processors & Controllers
Pins	20

CAD (KiCad official)

Symbol: STM32C011F6U6TR
Footprint: Package_DFN_QFN:ST_UFQFPN-20_3x3mm_P0.5mm
3D model: UFQFPN-20(3x3) (KiCad packages3D, STEP)
3D model files: stm32c011f6u6tr-etched.step / stm32c011f6u6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32c011f6u6tr.step / stm32c011f6u6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (94 pp, sha256 ae61483e03fb44f1, retrieved 2026-09-23, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF