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STL120N8F7-VB

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VBsemi Elec MOSFETs, DFN5x6-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorsstl120n8f7-vbfactory-2.0.0extractor-text

Verified STL120N8F7-VB

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 9 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: STL120N8F7-VB · DFN5x6-8 · 9 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 9 pin names found in the 7-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: DFN-S-8-1EP_6x5mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-omu3rh3q/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 9 pins = 9 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 9 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ stl120n8f7-vb.kicad_sym✓ stl120n8f7-vb.kicad_mod✓ stl120n8f7-vb.step
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

STL120N8F7-VB

VBsemi Elec · MOSFETs · DFN5x6-8

STL120N8F7-VB from VBsemi Elec, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the N-channel MOSFET (pins 1-3 are source), continuous source current up to 80 A.
2 S passive Source terminal of the N-channel MOSFET, tied with pins 1 and 3.
3 S passive Source terminal of the N-channel MOSFET, tied with pins 1 and 2.
4 G input Gate terminal with a maximum gate-source voltage of ±20 V.
5 D passive Drain terminal (pins 5-8 are drain), rated for 85 V drain-source breakdown.
6 D passive Drain terminal, tied with pins 5, 7 and 8.
7 D passive Drain terminal, tied with pins 5, 6 and 8.
8 D passive Drain terminal, tied with pins 5, 6 and 7.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package DFN5x6-8
Category Transistors/Thyristors
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage VDS 85 V VGS = 0 V, ID = 250 µA 2
Gate-Body Leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 20 V 2
Zero Gate Voltage Drain Current (TJ=125°C) IDSS 50 µA VDS = 30V, VGS = 0 V, TJ = 125 °C 2
On-State Drain Current ID(on) 60 A VDS = 5 V, VGS = 10 V 2
Forward Transconductance gfs 60 S VDS = 15 V, ID = 20 A 2
Input Capacitance Ciss 4200 pF VGS = 0 V, VDS = 85 V, f = 1 MHz 2
Output Capacitance Coss 470 pF VGS = 0 V, VDS = 85 V, f = 1 MHz 2
Reverse Transfer Capacitance Crss 225 pF VGS = 0 V, VDS = 85 V, f = 1 MHz 2
Pulsed Source Current ISM 240 A TC = 25 °C 2
Gate-Source Voltage VGS -20 20 V TC = 25 °C 1
Continuous Drain Current ID 64 A TC = 100 °C, TJ = 150 °C 1
Pulsed Drain Current IDM 240 A TC = 25 °C 1
Continuous Source Current (Diode Conduction) IS 80 A TC = 25 °C 1
Avalanche Current IAS 70 A L = 0.1 mH 1
Single Avalanche Energy EAS 133 mJ L = 0.1 mH, Duty Cycle ≤ 1 % 1
Maximum Power Dissipation PD 136 W TC = 25 °C 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Junction-to-Ambient, t ≤ 10 s RthJA 15 18 °C/W t ≤ 10 sec 1
Junction-to-Ambient, steady state RthJA 40 50 °C/W Steady State 1
Junction-to-Case RthJC 0.85 1.1 °C/W 1

CAD (KiCad official)

  • Symbol: STL120N8F7-VB
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: DFN5x6-8 (KiCad packages3D, STEP)
  • 3D model files: stl120n8f7-vb-etched.step / stl120n8f7-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stl120n8f7-vb.step / stl120n8f7-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (7 pp, sha256 1a86c0d797fb5318, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF