STL100N10F7-VB from VBsemi Elec, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	S	passive	Source terminal of the N-channel MOSFET (pin 1, marked with a dot on the package).
2	S	passive	Source terminal of the N-channel MOSFET, connected in parallel with pins 1 and 3.
3	S	passive	Source terminal of the N-channel MOSFET, connected in parallel with pins 1 and 2.
4	G	input	Gate terminal of the N-channel MOSFET, with a maximum gate-source voltage of ±20 V.
5	D	passive	Drain terminal of the 100 V N-channel MOSFET, connected in parallel with pins 6, 7 and 8.
6	D	passive	Drain terminal of the 100 V N-channel MOSFET, connected in parallel with pins 5, 7 and 8.
7	D	passive	Drain terminal of the 100 V N-channel MOSFET, connected in parallel with pins 5, 6 and 8.
8	D	passive	Drain terminal of the 100 V N-channel MOSFET, connected in parallel with pins 5, 6 and 7.
9	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	VBsemi Elec
Package	DFN5x6-8
Category	Transistors/Thyristors
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Gate-Source Voltage	VGS	-20		20	V	TC = 25 °C	1
Continuous Drain Current	ID			60	A	TJ = 175 °C, TC = 100 °C, package limited	1
Pulsed Drain Current	IDM			315	A	TC = 25 °C	1
Continuous Source Current (Diode Conduction)	IS			170	A	TC = 25 °C, package limited	1
Avalanche Current	IAS			60	A	TC = 25 °C	1
Single Avalanche Energy	EAS			110	mJ	Duty Cycle ≤ 1 %, L = 0.1 mH	1
Maximum Power Dissipation	PD			136	W	TC = 25 °C	1
Operating Junction and Storage Temperature Range	TJ, Tstg	-55		175	°C		1
Maximum Junction-to-Ambient (t ≤ 10 s)	RthJA		15	18	°C/W	t ≤ 10 sec	1
Maximum Junction-to-Ambient (Steady State)	RthJA		40	50	°C/W	Steady State	1
Maximum Junction-to-Case	RthJC		0.85	1.1	°C/W		1
Drain-Source Breakdown Voltage	VDS	100			V	VGS = 0 V, ID = 250 µA	2
Gate-Body Leakage	IGSS	-100		100	nA	VDS = 0 V, VGS = ± 20 V	2
Zero Gate Voltage Drain Current	IDSS			50	µA	VDS = 30V, VGS = 0 V, TJ = 125 °C	2
Zero Gate Voltage Drain Current	IDSS			250	µA	VDS = 30V, VGS = 0 V, TJ = 175 °C	2
On-State Drain Current	ID(on)	60			A	VDS = 5 V, VGS = 10 V	2
Pulsed Current	ISM			315	A	TC = 25 °C	2
Forward Transconductance	gfs		60		S	VDS = 15 V, ID = 20 A	2
Input Capacitance	Ciss		11000		pF	VGS = 0 V, VDS = 100 V, f = 1 MHz	2
Output Capacitance	Coss		470		pF	VGS = 0 V, VDS = 100 V, f = 1 MHz	2
Reverse Transfer Capacitance	Crss		225		pF	VGS = 0 V, VDS = 100 V, f = 1 MHz	2

CAD (KiCad official)

Symbol: STL100N10F7-VB
Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
3D model: DFN5x6-8 (KiCad packages3D, STEP)
3D model files: stl100n10f7-vb-etched.step / stl100n10f7-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stl100n10f7-vb.step / stl100n10f7-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: VBsemi Elec datasheet (7 pp, sha256 b7d0b5a374c25c0b, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

STL100N10F7-VB

Verified STL100N10F7-VB

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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