component

STISO620TR

Public Made by Adom

by adom

STMicroelectronics Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 23h ago
viewers stiso620tr: viewers · Ray 23h ago
package.json stiso620tr: LCSC part number C7089838 (was published as the bare integer) · Ray 9h ago
page.json stiso620tr: LCSC part number C7089838 (was published as the bare integer) · Ray 9h ago
README.md Initial commit: component/stiso620tr · Ray 23h ago
stiso620tr-etched.glb stiso620tr: factory component page (tier=lcsc) · Ray 23h ago
stiso620tr-etched.step stiso620tr: factory component page (tier=lcsc) · Ray 23h ago
stiso620tr-hero.glb Publish 0.1.0 · Ray 23h ago
stiso620tr-hero.overlay.json Publish 0.1.0 · Ray 23h ago
stiso620tr.glb Publish 0.1.0 · Ray 23h ago
stiso620tr.kicad_mod Publish 0.1.0 · Ray 23h ago
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stiso620tr.lbr Publish 0.1.0 · Ray 23h ago
stiso620tr.step Publish 0.1.0 · Ray 23h ago

STISO620TR

STMicroelectronics · Digital Isolators · SOIC-8

STISO620TR from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for transmit side, recommended operating range 3 V to 5.5 V with 2.75 V on-threshold
2 TXA input Transmit channel A logic input with Schmitt trigger thresholds of 0.8 V (low) and 2 V (high), supporting data rates up to 100 Mbps
3 TXB input Transmit channel B logic input with Schmitt trigger thresholds of 0.8 V (low) and 2 V (high), supporting data rates up to 100 Mbps
4 GND1 power_in Ground reference potential for transmit side
5 GND2 power_in Ground reference potential for receive side
6 RXB output Receive channel B logic output with 40-60 Ω output impedance, enters tri-state when VDD2 falls below UVLO threshold
7 RXA output Receive channel A logic output with 40-60 Ω output impedance, enters tri-state when VDD2 falls below UVLO threshold
8 VDD2 power_in Supply voltage for receive side, recommended operating range 3 V to 5.5 V with 2.75 V on-threshold

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-8
Category Signal Isolation Devices
Pins 8

CAD (KiCad official)

  • Symbol: STISO620TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: stiso620tr-etched.step / stiso620tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stiso620tr.step / stiso620tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (20 pp, sha256 c7836da97d08f2d5, retrieved 2026-10-06, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF